From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 18 Oct 2018 22:26:40 +0000 (+0100)
Subject: div
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9dad2f7adb0eedae1dfa3a7d28b76c7aa67e5449;p=riscv-isa-sim.git

div
---

diff --git a/riscv/insns/csrrwi.h b/riscv/insns/csrrwi.h
index 69c5472..eaeecd5 100644
--- a/riscv/insns/csrrwi.h
+++ b/riscv/insns/csrrwi.h
@@ -18,5 +18,5 @@ if (csr == CSR_USVVL || csr == CSR_USVMVL)
 reg_t old = p->get_csr(csr);
 p->set_csr(csr, insn.rs1());
 #endif
-WRITE_RD(sext_xlen(old));
+WRITE_RD(sext_xlen(sv_reg_t(old)));
 serialize();
diff --git a/riscv/insns/div.h b/riscv/insns/div.h
index b4dd9f2..0e44877 100644
--- a/riscv/insns/div.h
+++ b/riscv/insns/div.h
@@ -1,9 +1,9 @@
 require_extension('M');
-sreg_t lhs = sext_xlen(RS1);
-sreg_t rhs = sext_xlen(RS2);
-if(rhs == 0)
+sv_sreg_t lhs = sext_xlen(RS1);
+sv_sreg_t rhs = sext_xlen(RS2);
+if(rv_eq(rhs, sv_reg_t(0)))
   WRITE_RD(UINT64_MAX);
-else if(lhs == INT64_MIN && rhs == -1)
+else if(lhs == INT64_MIN && rv_eq(rhs, sv_reg_t(-1UL)))
   WRITE_RD(lhs);
 else
   WRITE_RD(sext_xlen(rv_div(lhs, rhs)));