From: R Veera Kumar <vklr@vkten.in>
Date: Thu, 25 Nov 2021 10:15:21 +0000 (+0530)
Subject: Shortened code in case_addis_nonzero_r0 alu test case
X-Git-Tag: sv_maxu_works-initial~698
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9dba54dce3b24e0800c34c59121403972e1cf6cc;p=openpower-isa.git

Shortened code in case_addis_nonzero_r0 alu test case
---

diff --git a/src/openpower/test/alu/alu_cases.py b/src/openpower/test/alu/alu_cases.py
index 5cb07aed..ca68fd2e 100644
--- a/src/openpower/test/alu/alu_cases.py
+++ b/src/openpower/test/alu/alu_cases.py
@@ -237,10 +237,7 @@ class ALUTestCase(TestAccumulatorBase):
             initial_regs[0] = random.randint(0, (1 << 64)-1)
             e = ExpectedState(pc=4)
             e.intregs[0] = initial_regs[0]
-            if imm < 0:
-                e.intregs[3] = (imm + 2**48)<<16
-            else:
-                e.intregs[3] = imm << 16
+            e.intregs[3] = (imm << 16) & ((1<<64)-1)
             self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 
     def case_rand_imm(self):