From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 4 Sep 2020 23:48:08 +0000 (+0100)
Subject: reduce CSR data width to 8 as an experiment
X-Git-Tag: semi_working_ecp5~199
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9dbaa7f67d3e3b3c48db5dc6ea91be57f91ff496;p=soc.git

reduce CSR data width to 8 as an experiment
---

diff --git a/src/soc/litex/florent/sim.py b/src/soc/litex/florent/sim.py
index 475314f2..460a85d5 100755
--- a/src/soc/litex/florent/sim.py
+++ b/src/soc/litex/florent/sim.py
@@ -96,7 +96,7 @@ class LibreSoCSim(SoCSDRAM):
             #bus_data_width           = 64,
             csr_address_width        = 12, # limit to 0x4000
             cpu_variant              = variant,
-            csr_data_width            = 32,
+            csr_data_width            = 8,
             l2_size             = 0,
             uart_name                = "sim",
             with_sdram               = with_sdram,