From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 27 Sep 2023 01:56:03 +0000 (-0700)
Subject: fix wrong register in docs
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9dbed6e82c8365a867ff6f608ae55b9e7688aa71;p=openpower-isa.git

fix wrong register in docs
---

diff --git a/src/openpower/test/bigint/bigint_cases.py b/src/openpower/test/bigint/bigint_cases.py
index 98ad5fda..2944ad43 100644
--- a/src/openpower/test/bigint/bigint_cases.py
+++ b/src/openpower/test/bigint/bigint_cases.py
@@ -163,7 +163,7 @@ class SVP64BigIntCases(TestAccumulatorBase):
         0x0000_0000_0500_0000 0x2800_0800_0800_0800 0x1fff_ffff_ffff_ffff
 
         with the 4-bit part that drops out of the 4 LSBs of r16 ending up
-        in r0
+        in r5
         """
         prog = Program(list(SVP64Asm(["sv.dsrd/mrr *16,*16,3,5"])), False)
         gprs = [0] * 32