From: whitequark Date: Mon, 3 Jun 2019 16:16:44 +0000 (+0000) Subject: examples: reorganize into examples/basic and examples/board. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9dc6451a32cc165562d4a499e3a2515da4c8e0a0;p=nmigen.git examples: reorganize into examples/basic and examples/board. --- diff --git a/examples/alu.py b/examples/alu.py deleted file mode 100644 index 5c0e8e6..0000000 --- a/examples/alu.py +++ /dev/null @@ -1,28 +0,0 @@ -from nmigen import * -from nmigen.cli import main - - -class ALU(Elaboratable): - def __init__(self, width): - self.sel = Signal(2) - self.a = Signal(width) - self.b = Signal(width) - self.o = Signal(width) - self.co = Signal() - - def elaborate(self, platform): - m = Module() - with m.If(self.sel == 0b00): - m.d.comb += self.o.eq(self.a | self.b) - with m.Elif(self.sel == 0b01): - m.d.comb += self.o.eq(self.a & self.b) - with m.Elif(self.sel == 0b10): - m.d.comb += self.o.eq(self.a ^ self.b) - with m.Else(): - m.d.comb += Cat(self.o, self.co).eq(self.a - self.b) - return m - - -if __name__ == "__main__": - alu = ALU(width=16) - main(alu, ports=[alu.sel, alu.a, alu.b, alu.o, alu.co]) diff --git a/examples/alu_hier.py b/examples/alu_hier.py deleted file mode 100644 index a3273af..0000000 --- a/examples/alu_hier.py +++ /dev/null @@ -1,58 +0,0 @@ -from nmigen import * -from nmigen.cli import main - - -class Adder(Elaboratable): - def __init__(self, width): - self.a = Signal(width) - self.b = Signal(width) - self.o = Signal(width) - - def elaborate(self, platform): - m = Module() - m.d.comb += self.o.eq(self.a + self.b) - return m - - -class Subtractor(Elaboratable): - def __init__(self, width): - self.a = Signal(width) - self.b = Signal(width) - self.o = Signal(width) - - def elaborate(self, platform): - m = Module() - m.d.comb += self.o.eq(self.a - self.b) - return m - - -class ALU(Elaboratable): - def __init__(self, width): - self.op = Signal() - self.a = Signal(width) - self.b = Signal(width) - self.o = Signal(width) - - self.add = Adder(width) - self.sub = Subtractor(width) - - def elaborate(self, platform): - m = Module() - m.submodules.add = self.add - m.submodules.sub = self.sub - m.d.comb += [ - self.add.a.eq(self.a), - self.sub.a.eq(self.a), - self.add.b.eq(self.b), - self.sub.b.eq(self.b), - ] - with m.If(self.op): - m.d.comb += self.o.eq(self.sub.o) - with m.Else(): - m.d.comb += self.o.eq(self.add.o) - return m - - -if __name__ == "__main__": - alu = ALU(width=16) - main(alu, ports=[alu.op, alu.a, alu.b, alu.o]) diff --git a/examples/arst.py b/examples/arst.py deleted file mode 100644 index ef3ed5a..0000000 --- a/examples/arst.py +++ /dev/null @@ -1,21 +0,0 @@ -from nmigen import * -from nmigen.cli import main - - -class ClockDivisor(Elaboratable): - def __init__(self, factor): - self.v = Signal(factor) - self.o = Signal() - - def elaborate(self, platform): - m = Module() - m.d.sync += self.v.eq(self.v + 1) - m.d.comb += self.o.eq(self.v[-1]) - return m - - -if __name__ == "__main__": - ctr = ClockDivisor(factor=16) - m = ctr.elaborate(platform=None) - m.domains += ClockDomain("sync", async_reset=True) - main(m, ports=[ctr.o]) diff --git a/examples/basic/alu.py b/examples/basic/alu.py new file mode 100644 index 0000000..5c0e8e6 --- /dev/null +++ b/examples/basic/alu.py @@ -0,0 +1,28 @@ +from nmigen import * +from nmigen.cli import main + + +class ALU(Elaboratable): + def __init__(self, width): + self.sel = Signal(2) + self.a = Signal(width) + self.b = Signal(width) + self.o = Signal(width) + self.co = Signal() + + def elaborate(self, platform): + m = Module() + with m.If(self.sel == 0b00): + m.d.comb += self.o.eq(self.a | self.b) + with m.Elif(self.sel == 0b01): + m.d.comb += self.o.eq(self.a & self.b) + with m.Elif(self.sel == 0b10): + m.d.comb += self.o.eq(self.a ^ self.b) + with m.Else(): + m.d.comb += Cat(self.o, self.co).eq(self.a - self.b) + return m + + +if __name__ == "__main__": + alu = ALU(width=16) + main(alu, ports=[alu.sel, alu.a, alu.b, alu.o, alu.co]) diff --git a/examples/basic/alu_hier.py b/examples/basic/alu_hier.py new file mode 100644 index 0000000..a3273af --- /dev/null +++ b/examples/basic/alu_hier.py @@ -0,0 +1,58 @@ +from nmigen import * +from nmigen.cli import main + + +class Adder(Elaboratable): + def __init__(self, width): + self.a = Signal(width) + self.b = Signal(width) + self.o = Signal(width) + + def elaborate(self, platform): + m = Module() + m.d.comb += self.o.eq(self.a + self.b) + return m + + +class Subtractor(Elaboratable): + def __init__(self, width): + self.a = Signal(width) + self.b = Signal(width) + self.o = Signal(width) + + def elaborate(self, platform): + m = Module() + m.d.comb += self.o.eq(self.a - self.b) + return m + + +class ALU(Elaboratable): + def __init__(self, width): + self.op = Signal() + self.a = Signal(width) + self.b = Signal(width) + self.o = Signal(width) + + self.add = Adder(width) + self.sub = Subtractor(width) + + def elaborate(self, platform): + m = Module() + m.submodules.add = self.add + m.submodules.sub = self.sub + m.d.comb += [ + self.add.a.eq(self.a), + self.sub.a.eq(self.a), + self.add.b.eq(self.b), + self.sub.b.eq(self.b), + ] + with m.If(self.op): + m.d.comb += self.o.eq(self.sub.o) + with m.Else(): + m.d.comb += self.o.eq(self.add.o) + return m + + +if __name__ == "__main__": + alu = ALU(width=16) + main(alu, ports=[alu.op, alu.a, alu.b, alu.o]) diff --git a/examples/basic/arst.py b/examples/basic/arst.py new file mode 100644 index 0000000..ef3ed5a --- /dev/null +++ b/examples/basic/arst.py @@ -0,0 +1,21 @@ +from nmigen import * +from nmigen.cli import main + + +class ClockDivisor(Elaboratable): + def __init__(self, factor): + self.v = Signal(factor) + self.o = Signal() + + def elaborate(self, platform): + m = Module() + m.d.sync += self.v.eq(self.v + 1) + m.d.comb += self.o.eq(self.v[-1]) + return m + + +if __name__ == "__main__": + ctr = ClockDivisor(factor=16) + m = ctr.elaborate(platform=None) + m.domains += ClockDomain("sync", async_reset=True) + main(m, ports=[ctr.o]) diff --git a/examples/basic/cdc.py b/examples/basic/cdc.py new file mode 100644 index 0000000..4f2dfad --- /dev/null +++ b/examples/basic/cdc.py @@ -0,0 +1,10 @@ +from nmigen import * +from nmigen.cli import main + + +i, o = Signal(name="i"), Signal(name="o") +m = Module() +m.submodules += MultiReg(i, o) + +if __name__ == "__main__": + main(m, ports=[i, o]) diff --git a/examples/basic/ctr.py b/examples/basic/ctr.py new file mode 100644 index 0000000..9752299 --- /dev/null +++ b/examples/basic/ctr.py @@ -0,0 +1,19 @@ +from nmigen import * +from nmigen.cli import main, pysim + + +class Counter(Elaboratable): + def __init__(self, width): + self.v = Signal(width, reset=2**width-1) + self.o = Signal() + + def elaborate(self, platform): + m = Module() + m.d.sync += self.v.eq(self.v + 1) + m.d.comb += self.o.eq(self.v[-1]) + return m + + +ctr = Counter(width=16) +if __name__ == "__main__": + main(ctr, ports=[ctr.o]) diff --git a/examples/basic/ctr_ce.py b/examples/basic/ctr_ce.py new file mode 100644 index 0000000..f839d67 --- /dev/null +++ b/examples/basic/ctr_ce.py @@ -0,0 +1,35 @@ +from nmigen import * +from nmigen.back import rtlil, verilog, pysim + + +class Counter(Elaboratable): + def __init__(self, width): + self.v = Signal(width, reset=2**width-1) + self.o = Signal() + self.ce = Signal() + + def elaborate(self, platform): + m = Module() + m.d.sync += self.v.eq(self.v + 1) + m.d.comb += self.o.eq(self.v[-1]) + return CEInserter(self.ce)(m.lower(platform)) + + +ctr = Counter(width=16) + +print(verilog.convert(ctr, ports=[ctr.o, ctr.ce])) + +with pysim.Simulator(ctr, + vcd_file=open("ctrl.vcd", "w"), + gtkw_file=open("ctrl.gtkw", "w"), + traces=[ctr.ce, ctr.v, ctr.o]) as sim: + sim.add_clock(1e-6) + def ce_proc(): + yield; yield; yield + yield ctr.ce.eq(1) + yield; yield; yield + yield ctr.ce.eq(0) + yield; yield; yield + yield ctr.ce.eq(1) + sim.add_sync_process(ce_proc()) + sim.run_until(100e-6, run_passive=True) diff --git a/examples/basic/fsm.py b/examples/basic/fsm.py new file mode 100644 index 0000000..73e6f7d --- /dev/null +++ b/examples/basic/fsm.py @@ -0,0 +1,64 @@ +from nmigen import * +from nmigen.cli import main + + +class UARTReceiver(Elaboratable): + def __init__(self, divisor): + self.divisor = divisor + + self.i = Signal() + self.data = Signal(8) + self.rdy = Signal() + self.ack = Signal() + self.err = Signal() + + def elaborate(self, platform): + m = Module() + + ctr = Signal(max=self.divisor) + stb = Signal() + with m.If(ctr == 0): + m.d.sync += ctr.eq(self.divisor - 1) + m.d.comb += stb.eq(1) + with m.Else(): + m.d.sync += ctr.eq(ctr - 1) + + bit = Signal(3) + with m.FSM() as fsm: + with m.State("START"): + with m.If(~self.i): + m.next = "DATA" + m.d.sync += [ + ctr.eq(self.divisor // 2), + bit.eq(7), + ] + with m.State("DATA"): + with m.If(stb): + m.d.sync += [ + bit.eq(bit - 1), + self.data.eq(Cat(self.i, self.data)) + ] + with m.If(bit == 0): + m.next = "STOP" + with m.State("STOP"): + with m.If(stb): + with m.If(self.i): + m.next = "DONE" + with m.Else(): + m.next = "ERROR" + + with m.State("DONE"): + m.d.comb += self.rdy.eq(1) + with m.If(self.ack): + m.next = "START" + + m.d.comb += self.err.eq(fsm.ongoing("ERROR")) + with m.State("ERROR"): + pass + + return m + + +if __name__ == "__main__": + rx = UARTReceiver(20) + main(rx, ports=[rx.i, rx.data, rx.rdy, rx.ack, rx.err]) diff --git a/examples/basic/gpio.py b/examples/basic/gpio.py new file mode 100644 index 0000000..3dd0da0 --- /dev/null +++ b/examples/basic/gpio.py @@ -0,0 +1,28 @@ +from types import SimpleNamespace +from nmigen import * +from nmigen.cli import main + + +class GPIO(Elaboratable): + def __init__(self, pins, bus): + self.pins = pins + self.bus = bus + + def elaborate(self, platform): + m = Module() + m.d.comb += self.bus.r_data.eq(self.pins[self.bus.addr]) + with m.If(self.bus.we): + m.d.sync += self.pins[self.bus.addr].eq(self.bus.w_data) + return m + + +if __name__ == "__main__": + bus = Record([ + ("addr", 3), + ("r_data", 1), + ("w_data", 1), + ("we", 1), + ]) + pins = Signal(8) + gpio = GPIO(Array(pins), bus) + main(gpio, ports=[pins, bus.addr, bus.r_data, bus.w_data, bus.we]) diff --git a/examples/basic/inst.py b/examples/basic/inst.py new file mode 100644 index 0000000..2fc519b --- /dev/null +++ b/examples/basic/inst.py @@ -0,0 +1,26 @@ +from nmigen import * +from nmigen.cli import main + + +class System(Elaboratable): + def __init__(self): + self.adr = Signal(16) + self.dat_r = Signal(8) + self.dat_w = Signal(8) + self.we = Signal() + + def elaborate(self, platform): + m = Module() + m.submodules.cpu = Instance("CPU", + p_RESET_ADDR=0xfff0, + i_d_adr =self.adr, + i_d_dat_r=self.dat_r, + o_d_dat_w=self.dat_w, + i_d_we =self.we, + ) + return m + + +if __name__ == "__main__": + sys = System() + main(sys, ports=[sys.adr, sys.dat_r, sys.dat_w, sys.we]) diff --git a/examples/basic/mem.py b/examples/basic/mem.py new file mode 100644 index 0000000..82105fc --- /dev/null +++ b/examples/basic/mem.py @@ -0,0 +1,29 @@ +from nmigen import * +from nmigen.cli import main + + +class RegisterFile(Elaboratable): + def __init__(self): + self.adr = Signal(4) + self.dat_r = Signal(8) + self.dat_w = Signal(8) + self.we = Signal() + self.mem = Memory(width=8, depth=16, init=[0xaa, 0x55]) + + def elaborate(self, platform): + m = Module() + m.submodules.rdport = rdport = self.mem.read_port() + m.submodules.wrport = wrport = self.mem.write_port() + m.d.comb += [ + rdport.addr.eq(self.adr), + self.dat_r.eq(rdport.data), + wrport.addr.eq(self.adr), + wrport.data.eq(self.dat_w), + wrport.en.eq(self.we), + ] + return m + + +if __name__ == "__main__": + rf = RegisterFile() + main(rf, ports=[rf.adr, rf.dat_r, rf.dat_w, rf.we]) diff --git a/examples/basic/pmux.py b/examples/basic/pmux.py new file mode 100644 index 0000000..1e938b5 --- /dev/null +++ b/examples/basic/pmux.py @@ -0,0 +1,29 @@ +from nmigen import * +from nmigen.cli import main + + +class ParMux(Elaboratable): + def __init__(self, width): + self.s = Signal(3) + self.a = Signal(width) + self.b = Signal(width) + self.c = Signal(width) + self.o = Signal(width) + + def elaborate(self, platform): + m = Module() + with m.Switch(self.s): + with m.Case("--1"): + m.d.comb += self.o.eq(self.a) + with m.Case("-1-"): + m.d.comb += self.o.eq(self.b) + with m.Case("1--"): + m.d.comb += self.o.eq(self.c) + with m.Case(): + m.d.comb += self.o.eq(0) + return m + + +if __name__ == "__main__": + pmux = ParMux(width=16) + main(pmux, ports=[pmux.s, pmux.a, pmux.b, pmux.c, pmux.o]) diff --git a/examples/basic/por.py b/examples/basic/por.py new file mode 100644 index 0000000..63eca23 --- /dev/null +++ b/examples/basic/por.py @@ -0,0 +1,19 @@ +from nmigen import * +from nmigen.cli import main + + +m = Module() +cd_por = ClockDomain(reset_less=True) +cd_sync = ClockDomain() +m.domains += cd_por, cd_sync + +delay = Signal(max=255, reset=255) +with m.If(delay != 0): + m.d.por += delay.eq(delay - 1) +m.d.comb += [ + ClockSignal().eq(cd_por.clk), + ResetSignal().eq(delay != 0), +] + +if __name__ == "__main__": + main(m, ports=[cd_por.clk]) diff --git a/examples/blinky.py b/examples/blinky.py deleted file mode 100644 index 3228163..0000000 --- a/examples/blinky.py +++ /dev/null @@ -1,21 +0,0 @@ -from nmigen import * -from nmigen.vendor.board.ice40_hx1k_blink_evn import * - - -class Blinky(Elaboratable): - def elaborate(self, platform): - clk3p3 = platform.request("clk3p3") - user_led = platform.request("user_led", 0) - counter = Signal(20) - - m = Module() - m.domains.sync = ClockDomain() - m.d.comb += ClockSignal().eq(clk3p3.i) - m.d.sync += counter.eq(counter + 1) - m.d.comb += user_led.o.eq(counter[-1]) - return m - - -if __name__ == "__main__": - platform = ICE40HX1KBlinkEVNPlatform() - platform.build(Blinky(), do_program=True) diff --git a/examples/board/blinky.py b/examples/board/blinky.py new file mode 100644 index 0000000..3228163 --- /dev/null +++ b/examples/board/blinky.py @@ -0,0 +1,21 @@ +from nmigen import * +from nmigen.vendor.board.ice40_hx1k_blink_evn import * + + +class Blinky(Elaboratable): + def elaborate(self, platform): + clk3p3 = platform.request("clk3p3") + user_led = platform.request("user_led", 0) + counter = Signal(20) + + m = Module() + m.domains.sync = ClockDomain() + m.d.comb += ClockSignal().eq(clk3p3.i) + m.d.sync += counter.eq(counter + 1) + m.d.comb += user_led.o.eq(counter[-1]) + return m + + +if __name__ == "__main__": + platform = ICE40HX1KBlinkEVNPlatform() + platform.build(Blinky(), do_program=True) diff --git a/examples/cdc.py b/examples/cdc.py deleted file mode 100644 index 4f2dfad..0000000 --- a/examples/cdc.py +++ /dev/null @@ -1,10 +0,0 @@ -from nmigen import * -from nmigen.cli import main - - -i, o = Signal(name="i"), Signal(name="o") -m = Module() -m.submodules += MultiReg(i, o) - -if __name__ == "__main__": - main(m, ports=[i, o]) diff --git a/examples/ctr.py b/examples/ctr.py deleted file mode 100644 index 9752299..0000000 --- a/examples/ctr.py +++ /dev/null @@ -1,19 +0,0 @@ -from nmigen import * -from nmigen.cli import main, pysim - - -class Counter(Elaboratable): - def __init__(self, width): - self.v = Signal(width, reset=2**width-1) - self.o = Signal() - - def elaborate(self, platform): - m = Module() - m.d.sync += self.v.eq(self.v + 1) - m.d.comb += self.o.eq(self.v[-1]) - return m - - -ctr = Counter(width=16) -if __name__ == "__main__": - main(ctr, ports=[ctr.o]) diff --git a/examples/ctr_ce.py b/examples/ctr_ce.py deleted file mode 100644 index f839d67..0000000 --- a/examples/ctr_ce.py +++ /dev/null @@ -1,35 +0,0 @@ -from nmigen import * -from nmigen.back import rtlil, verilog, pysim - - -class Counter(Elaboratable): - def __init__(self, width): - self.v = Signal(width, reset=2**width-1) - self.o = Signal() - self.ce = Signal() - - def elaborate(self, platform): - m = Module() - m.d.sync += self.v.eq(self.v + 1) - m.d.comb += self.o.eq(self.v[-1]) - return CEInserter(self.ce)(m.lower(platform)) - - -ctr = Counter(width=16) - -print(verilog.convert(ctr, ports=[ctr.o, ctr.ce])) - -with pysim.Simulator(ctr, - vcd_file=open("ctrl.vcd", "w"), - gtkw_file=open("ctrl.gtkw", "w"), - traces=[ctr.ce, ctr.v, ctr.o]) as sim: - sim.add_clock(1e-6) - def ce_proc(): - yield; yield; yield - yield ctr.ce.eq(1) - yield; yield; yield - yield ctr.ce.eq(0) - yield; yield; yield - yield ctr.ce.eq(1) - sim.add_sync_process(ce_proc()) - sim.run_until(100e-6, run_passive=True) diff --git a/examples/fsm.py b/examples/fsm.py deleted file mode 100644 index 73e6f7d..0000000 --- a/examples/fsm.py +++ /dev/null @@ -1,64 +0,0 @@ -from nmigen import * -from nmigen.cli import main - - -class UARTReceiver(Elaboratable): - def __init__(self, divisor): - self.divisor = divisor - - self.i = Signal() - self.data = Signal(8) - self.rdy = Signal() - self.ack = Signal() - self.err = Signal() - - def elaborate(self, platform): - m = Module() - - ctr = Signal(max=self.divisor) - stb = Signal() - with m.If(ctr == 0): - m.d.sync += ctr.eq(self.divisor - 1) - m.d.comb += stb.eq(1) - with m.Else(): - m.d.sync += ctr.eq(ctr - 1) - - bit = Signal(3) - with m.FSM() as fsm: - with m.State("START"): - with m.If(~self.i): - m.next = "DATA" - m.d.sync += [ - ctr.eq(self.divisor // 2), - bit.eq(7), - ] - with m.State("DATA"): - with m.If(stb): - m.d.sync += [ - bit.eq(bit - 1), - self.data.eq(Cat(self.i, self.data)) - ] - with m.If(bit == 0): - m.next = "STOP" - with m.State("STOP"): - with m.If(stb): - with m.If(self.i): - m.next = "DONE" - with m.Else(): - m.next = "ERROR" - - with m.State("DONE"): - m.d.comb += self.rdy.eq(1) - with m.If(self.ack): - m.next = "START" - - m.d.comb += self.err.eq(fsm.ongoing("ERROR")) - with m.State("ERROR"): - pass - - return m - - -if __name__ == "__main__": - rx = UARTReceiver(20) - main(rx, ports=[rx.i, rx.data, rx.rdy, rx.ack, rx.err]) diff --git a/examples/gpio.py b/examples/gpio.py deleted file mode 100644 index 3dd0da0..0000000 --- a/examples/gpio.py +++ /dev/null @@ -1,28 +0,0 @@ -from types import SimpleNamespace -from nmigen import * -from nmigen.cli import main - - -class GPIO(Elaboratable): - def __init__(self, pins, bus): - self.pins = pins - self.bus = bus - - def elaborate(self, platform): - m = Module() - m.d.comb += self.bus.r_data.eq(self.pins[self.bus.addr]) - with m.If(self.bus.we): - m.d.sync += self.pins[self.bus.addr].eq(self.bus.w_data) - return m - - -if __name__ == "__main__": - bus = Record([ - ("addr", 3), - ("r_data", 1), - ("w_data", 1), - ("we", 1), - ]) - pins = Signal(8) - gpio = GPIO(Array(pins), bus) - main(gpio, ports=[pins, bus.addr, bus.r_data, bus.w_data, bus.we]) diff --git a/examples/inst.py b/examples/inst.py deleted file mode 100644 index 2fc519b..0000000 --- a/examples/inst.py +++ /dev/null @@ -1,26 +0,0 @@ -from nmigen import * -from nmigen.cli import main - - -class System(Elaboratable): - def __init__(self): - self.adr = Signal(16) - self.dat_r = Signal(8) - self.dat_w = Signal(8) - self.we = Signal() - - def elaborate(self, platform): - m = Module() - m.submodules.cpu = Instance("CPU", - p_RESET_ADDR=0xfff0, - i_d_adr =self.adr, - i_d_dat_r=self.dat_r, - o_d_dat_w=self.dat_w, - i_d_we =self.we, - ) - return m - - -if __name__ == "__main__": - sys = System() - main(sys, ports=[sys.adr, sys.dat_r, sys.dat_w, sys.we]) diff --git a/examples/mem.py b/examples/mem.py deleted file mode 100644 index 82105fc..0000000 --- a/examples/mem.py +++ /dev/null @@ -1,29 +0,0 @@ -from nmigen import * -from nmigen.cli import main - - -class RegisterFile(Elaboratable): - def __init__(self): - self.adr = Signal(4) - self.dat_r = Signal(8) - self.dat_w = Signal(8) - self.we = Signal() - self.mem = Memory(width=8, depth=16, init=[0xaa, 0x55]) - - def elaborate(self, platform): - m = Module() - m.submodules.rdport = rdport = self.mem.read_port() - m.submodules.wrport = wrport = self.mem.write_port() - m.d.comb += [ - rdport.addr.eq(self.adr), - self.dat_r.eq(rdport.data), - wrport.addr.eq(self.adr), - wrport.data.eq(self.dat_w), - wrport.en.eq(self.we), - ] - return m - - -if __name__ == "__main__": - rf = RegisterFile() - main(rf, ports=[rf.adr, rf.dat_r, rf.dat_w, rf.we]) diff --git a/examples/pmux.py b/examples/pmux.py deleted file mode 100644 index 1e938b5..0000000 --- a/examples/pmux.py +++ /dev/null @@ -1,29 +0,0 @@ -from nmigen import * -from nmigen.cli import main - - -class ParMux(Elaboratable): - def __init__(self, width): - self.s = Signal(3) - self.a = Signal(width) - self.b = Signal(width) - self.c = Signal(width) - self.o = Signal(width) - - def elaborate(self, platform): - m = Module() - with m.Switch(self.s): - with m.Case("--1"): - m.d.comb += self.o.eq(self.a) - with m.Case("-1-"): - m.d.comb += self.o.eq(self.b) - with m.Case("1--"): - m.d.comb += self.o.eq(self.c) - with m.Case(): - m.d.comb += self.o.eq(0) - return m - - -if __name__ == "__main__": - pmux = ParMux(width=16) - main(pmux, ports=[pmux.s, pmux.a, pmux.b, pmux.c, pmux.o]) diff --git a/examples/por.py b/examples/por.py deleted file mode 100644 index 63eca23..0000000 --- a/examples/por.py +++ /dev/null @@ -1,19 +0,0 @@ -from nmigen import * -from nmigen.cli import main - - -m = Module() -cd_por = ClockDomain(reset_less=True) -cd_sync = ClockDomain() -m.domains += cd_por, cd_sync - -delay = Signal(max=255, reset=255) -with m.If(delay != 0): - m.d.por += delay.eq(delay - 1) -m.d.comb += [ - ClockSignal().eq(cd_por.clk), - ResetSignal().eq(delay != 0), -] - -if __name__ == "__main__": - main(m, ports=[cd_por.clk])