From: Florent Kermarrec Date: Sat, 20 Dec 2014 12:26:07 +0000 (+0100) Subject: add identify device to command_tb and revert endianness (seems conform with Lecroy... X-Git-Tag: 24jan2021_ls180~2572^2~84 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9dc6903c551347b957136fa372f20eb32e40243d;p=litex.git add identify device to command_tb and revert endianness (seems conform with Lecroy SATA Protocol suite samples) it seems endianness is correct by is only printed in LSB first in Lecroy software --- diff --git a/lib/sata/test/command_tb.py b/lib/sata/test/command_tb.py index fd6c3a1e..50397c3a 100644 --- a/lib/sata/test/command_tb.py +++ b/lib/sata/test/command_tb.py @@ -100,5 +100,8 @@ class TB(Module): s, l, e = check(write_data, read_data) print("shift "+ str(s) + " / length " + str(l) + " / errors " + str(e)) + identify_packet = CommandTXPacket(identify=1) + yield from self.streamer.send(identify_packet) + if __name__ == "__main__": run_simulation(TB(), ncycles=2048, vcd_name="my.vcd", keep_files=True) diff --git a/lib/sata/test/hdd.py b/lib/sata/test/hdd.py index 6a58518f..ec62bbcb 100644 --- a/lib/sata/test/hdd.py +++ b/lib/sata/test/hdd.py @@ -282,7 +282,7 @@ def _little2big(v): return r def get_field_data(field, packet): - return (_little2big(packet[field.dword]) >> field.offset) & (2**field.width-1) + return (packet[field.dword] >> field.offset) & (2**field.width-1) class FIS: def __init__(self, packet, description, direction="H2D"): @@ -297,7 +297,7 @@ class FIS: def encode(self): for k, v in self.description.items(): - self.packet[v.dword] |= _big2little((getattr(self, k) << v.offset)) + self.packet[v.dword] |= (getattr(self, k) << v.offset) def __repr__(self): if self.direction == "H2D": @@ -385,7 +385,7 @@ class TransportLayer(Module): print_transport(fis) def callback(self, packet): - fis_type = _little2big(packet[0]) & 0xff + fis_type = packet[0] & 0xff if fis_type == fis_types["REG_H2D"]: fis = FIS_REG_H2D(packet) elif fis_type == fis_types["REG_D2H"]: @@ -508,7 +508,8 @@ class HDD(Module): packet.insert(0, 0) return [FIS_DATA(packet, direction="D2H"), FIS_REG_D2H()] - def identify_dma_callback(self, fis): + def identify_device_dma_callback(self, fis): + print_hdd("Identify device request") packet = [i for i in range(256)] packet.insert(0, 0) return [FIS_DATA(packet, direction="D2H"), FIS_REG_D2H()] diff --git a/lib/sata/transport/__init__.py b/lib/sata/transport/__init__.py index 6abbfd5c..f83aa672 100644 --- a/lib/sata/transport/__init__.py +++ b/lib/sata/transport/__init__.py @@ -96,7 +96,7 @@ class SATATransportTX(Module): cmd_cases = {} for i in range(cmd_ndwords): - cmd_cases[i] = [link.sink.d.eq(_big2little(encoded_cmd[32*i:32*(i+1)]))] + cmd_cases[i] = [link.sink.d.eq(encoded_cmd[32*i:32*(i+1)])] self.comb += \ If(cmd_send, @@ -141,7 +141,7 @@ class SATATransportRX(Module): data_done = Signal() def test_type(name): - return link.source.d[24:] == fis_types[name] + return link.source.d[:8] == fis_types[name] self.fsm = fsm = FSM(reset_state="IDLE") @@ -230,7 +230,7 @@ class SATATransportRX(Module): cmd_cases = {} for i in range(cmd_ndwords): - cmd_cases[i] = [encoded_cmd[32*i:32*(i+1)].eq(_little2big(link.source.d))] + cmd_cases[i] = [encoded_cmd[32*i:32*(i+1)].eq(link.source.d)] self.comb += \ If(cmd_receive & link.source.stb,