From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 25 Jun 2019 04:52:53 +0000 (-0700)
Subject: Add tests/various/abc9.{v,ys} with SCC test
X-Git-Tag: working-ls180~1237^2~50
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9dca024a30e5f6cfb06e1abb584ce1320fb81f16;p=yosys.git

Add tests/various/abc9.{v,ys} with SCC test
---

diff --git a/tests/various/abc9.v b/tests/various/abc9.v
new file mode 100644
index 000000000..8271cd249
--- /dev/null
+++ b/tests/various/abc9.v
@@ -0,0 +1,5 @@
+module abc9_test027(output reg o);
+initial o = 1'b0;
+always @*
+    o <= ~o;
+endmodule
diff --git a/tests/various/abc9.ys b/tests/various/abc9.ys
new file mode 100644
index 000000000..922f7005d
--- /dev/null
+++ b/tests/various/abc9.ys
@@ -0,0 +1,14 @@
+read_verilog abc9.v
+proc
+design -save gold
+
+abc9 -lut 4
+check
+design -stash gate
+
+design -import gold -as gold
+design -import gate -as gate
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
+