From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 14 Jun 2014 05:44:19 +0000 (+0200)
Subject: Added real->int convertion in ast genrtlil
X-Git-Tag: yosys-0.4~613
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9dd16fa41c01c8da2e4905184cce0391a7547fa3;p=yosys.git

Added real->int convertion in ast genrtlil
---

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 9273636f4..5b43f57ff 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -602,6 +602,10 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint)
 			sign_hint = false;
 		break;
 
+	case AST_REALVALUE:
+		width_hint = std::max(width_hint, 32);
+		break;
+
 	case AST_IDENTIFIER:
 		id_ast = id2ast;
 		if (id_ast == NULL && current_scope.count(str))
@@ -909,6 +913,14 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 			return RTLIL::SigSpec(bitsAsConst());
 		}
 
+	case AST_REALVALUE:
+		{
+			int intvalue = round(realvalue);
+			log("Warning: converting real value %e to integer %d at %s:%d.\n",
+					realvalue, intvalue, filename.c_str(), linenum);
+			return RTLIL::SigSpec(intvalue);
+		}
+
 	// simply return the corresponding RTLIL::SigSpec for an AST_IDENTIFIER node
 	// for identifiers with dynamic bit ranges (e.g. "foo[bar]" or "foo[bar+3:bar]") a
 	// shifter cell is created and the output signal of this cell is returned