From: lkcl <lkcl@web>
Date: Wed, 5 Oct 2022 16:16:57 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~153
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9e0046bdcf80900448601709f62ec4260d250c2b;p=libreriscv.git

---

diff --git a/nlnet_2022_ongoing/discussion.mdwn b/nlnet_2022_ongoing/discussion.mdwn
index 6ab7a8577..aa9c3f850 100644
--- a/nlnet_2022_ongoing/discussion.mdwn
+++ b/nlnet_2022_ongoing/discussion.mdwn
@@ -8,9 +8,36 @@ context is from other [[nlnet_2022_opf_isa_wg/discussion]] on 2022-08-051
     (I'm assuming these are the same, but I've learned not to assume...)
 **
 
+yes EUR 3,000 / mo as a yardstick works out ok in practice.
+
+tasks, adapted (OpenCAPI is now a secret closed Standard, assigned to a
+group backed by Intel!)
+
+* 2-3 months: Dynamic Partitioned SIMD for nmigen 
+* 3-4 months: Completion of IEEE754 FP Formal Correctness Proofs
+* 3-5 months: Completion of an In-Order Single-Issue core implementing SVP64
+* 3-4 months: Addition of the IEEE754 FPU to the Core
+* 3-4 months: Addition of other ALUs and pipelines
+* 4-5 months: Addition of SMP (multi-core) support (lots of research here)
+* 3-4 months: Running under Verilator and on FPGAs (big ones) 
+* 4-5 months: Continued documentation, attendance of Conferences online
+* 4-5 months: Begin investigating Multi-Issue Out-of-Order
+* 2-3 months plus hosting costs: Establishment and management of CI
+* 2? months?: two Bitmain 250 FPGA porting (thanks to UOregon)
+
+lower estimate is around 33 months, upper limit is 44, so a EUR 100,000
+budget @ EUR 3,000/mo is within target (just). may need adjusting or some
+tasks removing, to fit. we cannot risk committing to tasks at too low a
+rate to be able to attract interest and committment.
+
 **
     What would be the concrete (high level) outcome of that project -
     where would the grant get us? Would there be a new test chip made
     during the lifespan of the project?
 **
 
+Answering on the ASIC first: it is a little early to tell.  Coriolis2 needs Timing
+based Routing completed in order to tackle lower geometries (even 90nm),
+https://libre-soc.org/nlnet_2021_lip6_vlsi/ 2021-08-049 - and sky130
+is far too small an allocation (12 mm^2 when we need around 100)
+