From: Luke Kenneth Casson Leighton Date: Wed, 8 May 2019 11:42:10 +0000 (+0100) Subject: make readable_i sync, stops infinite loop X-Git-Tag: div_pipeline~2097 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9e1629db9e61f7950a4cdbf64479063e87cf53ab;p=soc.git make readable_i sync, stops infinite loop --- diff --git a/src/experiment/cscore.py b/src/experiment/cscore.py index ed173c81..01e8506b 100644 --- a/src/experiment/cscore.py +++ b/src/experiment/cscore.py @@ -165,11 +165,12 @@ class Scoreboard(Elaboratable): # Connect Picker #--------- + # XXX sync, again to avoid an infinite loop. is it the right thing??? m.d.comb += intpick1.req_rel_i[0].eq(int_alus[0].req_rel_o) m.d.comb += intpick1.req_rel_i[1].eq(int_alus[1].req_rel_o) - m.d.comb += intpick1.readable_i[0].eq(il[0].int_readable_o) # add rdable + m.d.sync += intpick1.readable_i[0].eq(il[0].int_readable_o) # add rdable m.d.comb += intpick1.writable_i[0].eq(il[0].int_writable_o) # add rdable - m.d.comb += intpick1.readable_i[1].eq(il[1].int_readable_o) # sub rdable + m.d.sync += intpick1.readable_i[1].eq(il[1].int_readable_o) # sub rdable m.d.comb += intpick1.writable_i[1].eq(il[1].int_writable_o) # sub rdable #--------- @@ -242,7 +243,7 @@ def scoreboard_sim(dut): yield from int_instr(dut, IADD, 4, 3, 5) yield from print_reg(dut, [3,4,5]) yield - yield from int_instr(dut, IADD, 5, 2, 4) + yield from int_instr(dut, IADD, 5, 2, 5) yield from print_reg(dut, [3,4,5]) yield yield from int_instr(dut, ISUB, 5, 2, 3)