From: Gabe Black <gblack@eecs.umich.edu>
Date: Mon, 13 Oct 2008 03:25:06 +0000 (-0700)
Subject: X86: Let segment manipulation microops be conditional.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9e1fe2050ac55c28b6601770014193321a4013d0;p=gem5.git

X86: Let segment manipulation microops be conditional.
---

diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index dfb0abeae..4f93fad80 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -978,7 +978,7 @@ let {{
             '''
 
     # Microops for manipulating segmentation registers
-    class SegOp(RegOp):
+    class SegOp(CondRegOp):
         abstract = True
         def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
             super(SegOp, self).__init__(dest, \