From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 10 May 2019 05:12:34 +0000 (+0100)
Subject: derive from Elaboratable
X-Git-Tag: div_pipeline~2081
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9e20eb78efddb404a3f7c044c8dc451563707004;p=soc.git

derive from Elaboratable
---

diff --git a/src/TLB/AddressEncoder.py b/src/TLB/AddressEncoder.py
index 4c4b8d76..128f2c97 100644
--- a/src/TLB/AddressEncoder.py
+++ b/src/TLB/AddressEncoder.py
@@ -1,7 +1,7 @@
-from nmigen import Module, Signal
+from nmigen import Module, Signal, Elaboratable
 from nmigen.lib.coding import Encoder, PriorityEncoder
 
-class AddressEncoder():
+class AddressEncoder(Elaboratable):
     """Address Encoder
 
        The purpose of this module is to take in a vector and
diff --git a/src/TLB/Cam.py b/src/TLB/Cam.py
index 46ba27bd..e7d901ff 100644
--- a/src/TLB/Cam.py
+++ b/src/TLB/Cam.py
@@ -1,4 +1,4 @@
-from nmigen import Array, Cat, Module, Signal
+from nmigen import Array, Cat, Module, Signal, Elaboratable
 from nmigen.lib.coding import Decoder
 from nmigen.cli import main #, verilog
 
@@ -6,7 +6,7 @@ from .CamEntry import CamEntry
 from .AddressEncoder import AddressEncoder
 
 
-class Cam():
+class Cam(Elaboratable):
     """ Content Addressable Memory (CAM)
 
         The purpose of this module is to quickly look up whether an
diff --git a/src/TLB/CamEntry.py b/src/TLB/CamEntry.py
index 73081ce5..b1d93082 100644
--- a/src/TLB/CamEntry.py
+++ b/src/TLB/CamEntry.py
@@ -1,6 +1,7 @@
-from nmigen import Module, Signal
+from nmigen import Module, Signal, Elaboratable
 
-class CamEntry:
+
+class CamEntry(Elaboratable):
     """ Content Addressable Memory (CAM) Entry
 
         The purpose of this module is to represent an entry within a CAM.
diff --git a/src/TLB/PermissionValidator.py b/src/TLB/PermissionValidator.py
index e3058cb2..0107c0e9 100644
--- a/src/TLB/PermissionValidator.py
+++ b/src/TLB/PermissionValidator.py
@@ -1,9 +1,10 @@
-from nmigen import Module, Signal
+from nmigen import Module, Signal, Elaboratable
 from nmigen.cli import main
 
-from .PteEntry import PteEntry
+from TLB.PteEntry import PteEntry
 
-class PermissionValidator():
+
+class PermissionValidator(Elaboratable):
     """ The purpose of this Module is to check the Permissions of a given PTE
         against the requested access permissions.
 
diff --git a/src/TLB/PteEntry.py b/src/TLB/PteEntry.py
index c0705457..73ea9220 100644
--- a/src/TLB/PteEntry.py
+++ b/src/TLB/PteEntry.py
@@ -1,7 +1,8 @@
-from nmigen import Module, Signal
+from nmigen import Module, Signal, Elaboratable
 from nmigen.cli import main
 
-class PteEntry():
+
+class PteEntry(Elaboratable):
     """ The purpose of this Module is to  centralize the parsing of Page
         Table Entries (PTE) into one module to prevent common mistakes
         and duplication of code. The control bits are parsed out for
@@ -63,4 +64,4 @@ class PteEntry():
         ]
         m.d.comb += self.asid.eq(self.i[self.asid_start:self.asid_end])
         m.d.comb += self.pte.eq(self.i[0:self.asid_start])
-        return m
\ No newline at end of file
+        return m