From: Cesar Strauss <cestrauss@gmail.com>
Date: Mon, 25 May 2020 19:11:03 +0000 (-0300)
Subject: Move process list to CompUnitParallelTest
X-Git-Tag: div_pipeline~822
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9e23ee5194ec774923d90f816677a9bab2a83c71;p=soc.git

Move process list to CompUnitParallelTest

The process list (implementation detail) is best left for the class.
---

diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py
index 2764f76b..33a2492b 100644
--- a/src/soc/experiment/compalu_multi.py
+++ b/src/soc/experiment/compalu_multi.py
@@ -427,6 +427,16 @@ class CompUnitParallelTest:
         # TODO: also when dut.wr.go is set, check the output against the
         # self.expected_o and assert.  use dut.get_out(wr_idx) to do so.
 
+    def run_simulation(self, vcd_name):
+        run_simulation(self.dut, [self.driver(),
+                                  self.monitor(),
+                                  self.rd(0),  # one read port (a)
+                                  self.rd(1),  # one read port (b)
+                                  self.wr(0),  # one write port (o)
+                                  ],
+                       vcd_name=vcd_name)
+
+
 def test_compunit_regspec1():
     from alu_hier import ALU
     from soc.fu.alu.alu_input_record import CompALUOpSubset
@@ -451,13 +461,7 @@ def test_compunit_regspec1():
                    vcd_name='test_compunit_regspec1.vcd')
 
     test = CompUnitParallelTest(dut)
-    run_simulation(dut, [test.driver(),
-                         test.monitor(),
-                         test.rd(0), # one read port (a)
-                         test.rd(1), # one read port (b)
-                         test.wr(0)  # one write port (o)
-                        ],
-                   vcd_name="test_compunit_parallel.vcd")
+    test.run_simulation("test_compunit_parallel.vcd")
 
 
 if __name__ == '__main__':