From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 6 Jul 2020 22:26:56 +0000 (+0100)
Subject: remove alu unneeded op record data
X-Git-Tag: div_pipeline~162^2~16
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9e249b702c68308659823b9e9dd4920cde5de5fb;p=soc.git

remove alu unneeded op record data
---

diff --git a/src/soc/fu/alu/alu_input_record.py b/src/soc/fu/alu/alu_input_record.py
index 9d6afc20..70e4a9c2 100644
--- a/src/soc/fu/alu/alu_input_record.py
+++ b/src/soc/fu/alu/alu_input_record.py
@@ -22,8 +22,6 @@ class CompALUOpSubset(Record):
                   ('write_cr0', 1),
                   ('input_carry', CryIn),
                   ('output_carry', 1),
-                  ('input_cr', 1),
-                  ('output_cr', 1),
                   ('is_32bit', 1),
                   ('is_signed', 1),
                   ('data_len', 4), # actually used by ALU, in OP_EXTS
@@ -40,8 +38,6 @@ class CompALUOpSubset(Record):
         self.invert_out.reset_less = True
         self.input_carry.reset_less = True
         self.output_carry.reset_less = True
-        self.input_cr.reset_less = True
-        self.output_cr.reset_less = True
         self.is_32bit.reset_less = True
         self.is_signed.reset_less = True
         self.data_len.reset_less = True
@@ -61,8 +57,6 @@ class CompALUOpSubset(Record):
                 self.invert_out,
                 self.input_carry,
                 self.output_carry,
-                self.input_cr,
-                self.output_cr,
                 self.is_32bit,
                 self.is_signed,
                 self.data_len,