From: lkcl <lkcl@web>
Date: Sun, 23 Jun 2019 12:55:22 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~4529
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9e25864a4b0bf671ab53743e95cb9a0428d440b3;p=libreriscv.git

---

diff --git a/simple_v_extension/sv_prefix_proposal.rst b/simple_v_extension/sv_prefix_proposal.rst
index 8d4aca82b..10e8143a0 100644
--- a/simple_v_extension/sv_prefix_proposal.rst
+++ b/simple_v_extension/sv_prefix_proposal.rst
@@ -562,7 +562,7 @@ by twin-predication, register might be, by virtue of predicates being registers*
 
 Add a register gather instruction (aka MV.X: regfile[rd] = regfile[regfile[rs1]])
 
-# Open questions <a name="questions"></a>
+# questions
 
 Confirmation needed as to whether subvector extraction can be covered by twin predication (it probably can, it is one of the many purposes it is for).