From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 22 Aug 2019 15:06:24 +0000 (-0700)
Subject: Add cover()
X-Git-Tag: working-ls180~1111^2~3
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9e31f01b343a9b246430419e81da647e75bd1626;p=yosys.git

Add cover()
---

diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index 7fdfa82bd..aca15e5f2 100644
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -754,6 +754,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 			}
 
 			if (width < GetSize(sig_a)) {
+				cover("opt.opt_expr.trim_shiftx");
 				sig_a.remove(width, GetSize(sig_a)-width);
 				cell->setPort(ID::A, sig_a);
 				cell->setParam(ID(A_WIDTH), width);