From: Michael Nolan <mtnolan2640@gmail.com>
Date: Wed, 13 May 2020 14:07:56 +0000 (-0400)
Subject: Update TODO
X-Git-Tag: div_pipeline~1266
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9e524ef1f78556c24a1d31489aaf4c9b7a74db56;p=soc.git

Update TODO
---

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index e2a4f89d..2dc6205e 100644
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -178,10 +178,11 @@ class ISACaller:
         #            note that mffs, mcrfs, mtfsf "manage" this FPSCR
         # 2.3.1 CR (and sub-fields CR0..CR6 - CR0 SO comes from XER.SO)
         #         note that mfocrf, mfcr, mtcr, mtocrf, mcrxrx "manage" CRs
-        # 2.3.2 LR   (actually SPR #8)
-        # 2.3.3 CTR  (actually SPR #9)
+        #         -- Done
+        # 2.3.2 LR   (actually SPR #8) -- Done
+        # 2.3.3 CTR  (actually SPR #9) -- Done
         # 2.3.4 TAR  (actually SPR #815)
-        # 3.2.2 p45 XER  (actually SPR #0)
+        # 3.2.2 p45 XER  (actually SPR #1) -- Done
         # 3.2.3 p46 p232 VRSAVE (actually SPR #256)
 
         # create CR then allow portions of it to be "selectable" (below)