From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 2 Jan 2022 14:24:48 +0000 (+0000)
Subject: add ability to override the default RESET address (commented-out)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9e72b06ad34561248e4cdc3ec9361f2175500968;p=microwatt.git

add ability to override the default RESET address (commented-out)
also add extra settings to generic top-level to add UART1 if required
---

diff --git a/core.vhdl b/core.vhdl
index e2a93b9..41b7b45 100644
--- a/core.vhdl
+++ b/core.vhdl
@@ -13,6 +13,7 @@ entity core is
         EX1_BYPASS : boolean := true;
         HAS_FPU : boolean := true;
         HAS_BTC : boolean := true;
+	RESET_ADDRESS : std_ulogic_vector(63 downto 0) := (others => '0');
 	ALT_RESET_ADDRESS : std_ulogic_vector(63 downto 0) := (others => '0');
         LOG_LENGTH : natural := 512
         );
@@ -192,7 +193,7 @@ begin
 
     fetch1_0: entity work.fetch1
         generic map (
-            RESET_ADDRESS => (others => '0'),
+            RESET_ADDRESS => RESET_ADDRESS,
 	    ALT_RESET_ADDRESS => ALT_RESET_ADDRESS,
             HAS_BTC => HAS_BTC
             )
diff --git a/fpga/top-generic.vhdl b/fpga/top-generic.vhdl
index a9fb34e..70f938e 100644
--- a/fpga/top-generic.vhdl
+++ b/fpga/top-generic.vhdl
@@ -17,7 +17,8 @@ entity toplevel is
         HAS_BTC       : boolean  := false;
         LOG_LENGTH    : natural := 512;
 	DISABLE_FLATTEN_CORE : boolean := false;
-        UART_IS_16550 : boolean  := true
+        UART_IS_16550 : boolean  := true;
+        HAS_UART1          : boolean  := false
 	);
     port(
 	ext_clk   : in  std_ulogic;
@@ -86,7 +87,8 @@ begin
             HAS_BTC       => HAS_BTC,
             LOG_LENGTH    => LOG_LENGTH,
 	    DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE,
-            UART0_IS_16550     => UART_IS_16550
+            UART0_IS_16550     => UART_IS_16550,
+            HAS_UART1     => HAS_UART1
 	    )
 	port map (
 	    system_clk        => system_clk,
diff --git a/soc.vhdl b/soc.vhdl
index 352cfca..d72a009 100644
--- a/soc.vhdl
+++ b/soc.vhdl
@@ -59,6 +59,9 @@ entity soc is
 	HAS_DRAM           : boolean  := false;
 	SIM_MAIN_BRAM      : boolean  := false;
 	DRAM_SIZE          : integer := 0;
+    RESET_ADDRESS : std_ulogic_vector(63 downto 0) := (others => '0');
+    -- hack to jump-start alternative (e.g. verilator-loaded linux kernel)
+    -- RESET_ADDRESS : std_ulogic_vector(63 downto 0) := (22 downto 21 => '1', others => '0');
         DRAM_INIT_SIZE     : integer := 0;
         HAS_SPI_FLASH      : boolean := false;
         SPI_FLASH_DLINES   : positive := 1;
@@ -268,6 +271,7 @@ begin
             HAS_FPU => HAS_FPU,
             HAS_BTC => HAS_BTC,
 	    DISABLE_FLATTEN => DISABLE_FLATTEN_CORE,
+        RESET_ADDRESS => RESET_ADDRESS,
 	    ALT_RESET_ADDRESS => (23 downto 0 => '0', others => '1'),
             LOG_LENGTH => LOG_LENGTH
 	    )