From: lkcl <lkcl@web>
Date: Fri, 21 Apr 2023 00:05:54 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9e87f1093b210aae7d95d64e785cedc13d9fcef6;p=libreriscv.git

---

diff --git a/openpower/sv/po9_encoding.mdwn b/openpower/sv/po9_encoding.mdwn
index a06384935..b83989927 100644
--- a/openpower/sv/po9_encoding.mdwn
+++ b/openpower/sv/po9_encoding.mdwn
@@ -46,7 +46,7 @@ files horizontally, where moving to the next instruction is a clear priority.
 A 32-bit Prefix in front of a Defined Word that extends register
 numbers (allows larger register files), adds single-bit predication,
 element-width overrides, and optionally adds Saturation to Arithmetic
-instructions that normally would not have it.  *SVP64 is in Draft only*
+instructions that normally would not have it.  *SVP64Single is in Draft only*
 and is yet to be defined.
 
 **Definition of "UnVectoriseable":**