From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 3 Feb 2014 23:57:11 +0000 (+0100)
Subject: presentation progress
X-Git-Tag: yosys-0.2.0~102
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9e938aa32ad2b03eb9a9ea3bc1702ec4683cc37b;p=yosys.git

presentation progress
---

diff --git a/manual/PRESENTATION_ExSyn.tex b/manual/PRESENTATION_ExSyn.tex
index f2594487a..f67b502b2 100644
--- a/manual/PRESENTATION_ExSyn.tex
+++ b/manual/PRESENTATION_ExSyn.tex
@@ -267,7 +267,7 @@ memory -nomap; techmap -map my_memory_map.v; memory_map
 \end{lstlisting}
 \end{frame}
 
-\begin{frame}[t, fragile]{\subsecname{} -- Example 1/TBD}
+\begin{frame}[t, fragile]{\subsecname{} -- Example 1/2}
 \vbox to 0cm{\includegraphics[width=\linewidth,trim=0cm 0cm 0cm -10cm]{PRESENTATION_ExSyn/memory_01.pdf}\vss}
 \vskip-1cm
 \begin{columns}
@@ -278,7 +278,7 @@ memory -nomap; techmap -map my_memory_map.v; memory_map
 \end{columns}
 \end{frame}
 
-\begin{frame}[t, fragile]{\subsecname{} -- Example 2/TBD}
+\begin{frame}[t, fragile]{\subsecname{} -- Example 2/2}
 \vbox to 0cm{\hfill\includegraphics[width=7.5cm,trim=0cm 0cm 0cm -6cm]{PRESENTATION_ExSyn/memory_02.pdf}\vss}
 \vskip-1cm
 \begin{columns}
@@ -293,8 +293,52 @@ memory -nomap; techmap -map my_memory_map.v; memory_map
 
 \subsection{The ``fsm'' commands}
 
-\begin{frame}{\subsecname}
-TBD
+\begin{frame}[fragile]{\subsecname{}}
+The {\tt fsm} command identifies, extracts, optimizes (re-encodes), and
+re-synthesizes finite state machines. It again is a macro that calls
+a series of other commands:
+
+\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont]
+fsm_detect          # unless got option -nodetect
+fsm_extract
+
+fsm_opt
+opt_clean
+fsm_opt
+
+fsm_expand          # if got option -expand
+opt_clean           # if got option -expand
+fsm_opt             # if got option -expand
+
+fsm_recode          # unless got option -norecode
+
+fsm_info
+
+fsm_export          # if got option -export
+fsm_map             # unless got option -nomap
+\end{lstlisting}
+\end{frame}
+
+\begin{frame}{\subsecname{} -- details}
+Some details on the most importand commands from the {\tt fsm\_*} group:
+
+\bigskip
+The {\tt fsm\_detect} command identifies FSM state registers and marks them
+with the {\tt (* fsm\_encoding = "auto" *)} attribute, if they do not have the
+{\tt fsm\_encoding} set already. Mark registers with {\tt (* fsm\_encoding =
+"none" *)} to disable FSM optimization for a register.
+
+\bigskip
+The {\tt fsm\_extract} command replaces the entire FSM (logic and state
+registers) with a {\tt \$fsm} cell.
+
+\bigskip
+The commands {\tt fsm\_opt} and {\tt fsm\_recode} can be used to optimize the
+FSM.
+
+\bigskip
+Finally the {\tt fsm\_map} command can be used to convert the (optimized) {\tt
+\$fsm} cell back to logic and registers.
 \end{frame}
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
diff --git a/manual/presentation.tex b/manual/presentation.tex
index 06f80fc63..f9d40681a 100644
--- a/manual/presentation.tex
+++ b/manual/presentation.tex
@@ -92,15 +92,15 @@ synthesis. It supports most of Verilog-2005 and is well tested with
 real-world designs from the ASIC and FPGA world.
 
 \bigskip
-Learn how to use Yosys to create your own custom synthesis flows and discover
-why open source HDL synthesis is important for researchers, hobbyists,
-educators and engineers alike.
+Learn how to use Yosys to create your own custom synthesis flows and
+discover why open source HDL synthesis is important for researchers,
+hobbyists, educators and engineers alike.
 
 \bigskip
-This presentation covers basic concepts of Yosys, creating simple synthesis
-scripts, creating synthesis scripts for advanced applications, creating Yosys
-scripts for non-synthesis applications (such as formal equivialence checking)
-and writing extensions to Yosys using the C++ API.
+This presentation covers basic concepts of Yosys, writing synthesis scripts
+for a wide range of applications, creating Yosys scripts for various
+non-synthesis applications (such as formal equivialence checking) and
+writing extensions to Yosys using the C++ API.
 \end{frame}
 
 \section{Outline}