From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 4 Jun 2020 11:53:41 +0000 (+0100)
Subject: missing a fastregs write-port
X-Git-Tag: div_pipeline~611
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9eb3039d3fb8c65b79e8a81ed83b6e0fe23e9a3c;p=soc.git

missing a fastregs write-port
---

diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py
index 895739a1..5ba3b917 100644
--- a/src/soc/regfile/regfiles.py
+++ b/src/soc/regfile/regfiles.py
@@ -63,7 +63,8 @@ class FastRegs(RegFileArray):
     def __init__(self):
         super().__init__(64, 8)
         self.w_ports = [self.write_port("dest1"),
-                        self.write_port("dest2")]
+                        self.write_port("dest2"),
+                        self.write_port("dest3")]
         self.r_ports = [self.read_port("src1"),
                         self.read_port("src2"),
                         self.read_port("src3")]