From: Tim Newsome <tim@sifive.com>
Date: Wed, 20 Dec 2017 23:00:01 +0000 (-0800)
Subject: Remove `set arch riscv:rv%d`
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9eb3b8d3fcc7a491121c186e3a35022e11bb5653;p=riscv-tests.git

Remove `set arch riscv:rv%d`

gdb gets target XLEN from register width now, so this is taken care of
automatically.
---

diff --git a/debug/testlib.py b/debug/testlib.py
index 39a6fc4..ce8aeca 100644
--- a/debug/testlib.py
+++ b/debug/testlib.py
@@ -800,7 +800,6 @@ class GdbTest(BaseTest):
         self.logs += self.gdb.lognames()
         self.gdb.connect()
 
-        self.gdb.global_command("set arch riscv:rv%d" % self.hart.xlen)
         self.gdb.global_command("set remotetimeout %d" %
             self.target.timeout_sec)