From: whitequark Date: Tue, 18 Dec 2018 19:15:44 +0000 (+0000) Subject: hdl.ast: Cat.{operands→parts} X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9ebf08f3126139f66eba896dba0c32b3924a2afd;p=nmigen.git hdl.ast: Cat.{operands→parts} --- diff --git a/doc/COMPAT_SUMMARY.md b/doc/COMPAT_SUMMARY.md index 70f1545..86ba8f9 100644 --- a/doc/COMPAT_SUMMARY.md +++ b/doc/COMPAT_SUMMARY.md @@ -66,7 +66,7 @@ Compatibility summary - (+) `Mux` id - (+) `_Slice` → `Slice`, `stop=`→`end=`, `.stop`→`.end` - (+) `_Part` → `Part` - - (+) `Cat` id, `.l`→`.operands` + - (+) `Cat` id, `.l`→`.parts` - (+) `Replicate` → `Repl`, `v=`→`value=`, `n=`→`count=`, `.v`→`.value`, `.n`→`.count` - (+) `Constant` → `Const`, `bits_sign=`→`shape=` - (+) `Signal` id, `bits_sign=`→`shape=`, `attr=`→`attrs=`, `name_override=`∼, `related=`, `variable=`∼ diff --git a/nmigen/back/pysim.py b/nmigen/back/pysim.py index 206f199..7baa654 100644 --- a/nmigen/back/pysim.py +++ b/nmigen/back/pysim.py @@ -165,7 +165,7 @@ class _RHSValueCompiler(AbstractValueTransformer): shape = value.shape() parts = [] offset = 0 - for opnd in value.operands: + for opnd in value.parts: parts.append((offset, (1 << len(opnd)) - 1, self(opnd))) offset += len(opnd) def eval(state): @@ -248,7 +248,7 @@ class _LHSValueCompiler(AbstractValueTransformer): def on_Cat(self, value): parts = [] offset = 0 - for opnd in value.operands: + for opnd in value.parts: parts.append((offset, (1 << len(opnd)) - 1, self(opnd))) offset += len(opnd) def eval(state, rhs): diff --git a/nmigen/hdl/ast.py b/nmigen/hdl/ast.py index b9a7d7a..e890b4a 100644 --- a/nmigen/hdl/ast.py +++ b/nmigen/hdl/ast.py @@ -437,19 +437,19 @@ class Cat(Value): """ def __init__(self, *args): super().__init__() - self.operands = [Value.wrap(v) for v in flatten(args)] + self.parts = [Value.wrap(v) for v in flatten(args)] def shape(self): - return sum(len(op) for op in self.operands), False + return sum(len(op) for op in self.parts), False def _lhs_signals(self): - return union(op._lhs_signals() for op in self.operands) + return union(op._lhs_signals() for op in self.parts) def _rhs_signals(self): - return union(op._rhs_signals() for op in self.operands) + return union(op._rhs_signals() for op in self.parts) def __repr__(self): - return "(cat {})".format(" ".join(map(repr, self.operands))) + return "(cat {})".format(" ".join(map(repr, self.parts))) class Repl(Value): diff --git a/nmigen/hdl/xfrm.py b/nmigen/hdl/xfrm.py index a87a524..4c7f2b3 100644 --- a/nmigen/hdl/xfrm.py +++ b/nmigen/hdl/xfrm.py @@ -113,7 +113,7 @@ class ValueTransformer(AbstractValueTransformer): return Part(self.on_value(value.value), self.on_value(value.offset), value.width) def on_Cat(self, value): - return Cat(self.on_value(o) for o in value.operands) + return Cat(self.on_value(o) for o in value.parts) def on_Repl(self, value): return Repl(self.on_value(value.value), value.count) diff --git a/nmigen/test/test_hdl_ast.py b/nmigen/test/test_hdl_ast.py index 85e72f0..bf6b0fd 100644 --- a/nmigen/test/test_hdl_ast.py +++ b/nmigen/test/test_hdl_ast.py @@ -42,15 +42,15 @@ class ValueTestCase(FHDLTestCase): self.assertEqual(s2.end, 2) s3 = Const(31)[::2] self.assertIsInstance(s3, Cat) - self.assertIsInstance(s3.operands[0], Slice) - self.assertEqual(s3.operands[0].start, 0) - self.assertEqual(s3.operands[0].end, 1) - self.assertIsInstance(s3.operands[1], Slice) - self.assertEqual(s3.operands[1].start, 2) - self.assertEqual(s3.operands[1].end, 3) - self.assertIsInstance(s3.operands[2], Slice) - self.assertEqual(s3.operands[2].start, 4) - self.assertEqual(s3.operands[2].end, 5) + self.assertIsInstance(s3.parts[0], Slice) + self.assertEqual(s3.parts[0].start, 0) + self.assertEqual(s3.parts[0].end, 1) + self.assertIsInstance(s3.parts[1], Slice) + self.assertEqual(s3.parts[1].start, 2) + self.assertEqual(s3.parts[1].end, 3) + self.assertIsInstance(s3.parts[2], Slice) + self.assertEqual(s3.parts[2].start, 4) + self.assertEqual(s3.parts[2].end, 5) def test_getitem_wrong(self): with self.assertRaises(TypeError):