From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 4 Jun 2020 13:21:42 +0000 (+0100)
Subject: sync onto fu.go_wr_i otherwise a loop occurs
X-Git-Tag: div_pipeline~605
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9ec9396e85c84403acd8f01537a5f202d3aa1697;p=soc.git

sync onto fu.go_wr_i otherwise a loop occurs
---

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index a6fc30ce..95aed902 100644
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -50,7 +50,7 @@ class NonProductionCore(Elaboratable):
 
     def elaborate(self, platform):
         m = Module()
-        comb = m.d.comb
+        comb, sync = m.d.comb, m.d.sync
 
         m.submodules.pdecode2 = dec2 = self.pdecode2
         m.submodules.fus = self.fus
@@ -179,7 +179,7 @@ class NonProductionCore(Elaboratable):
                     fu_active = fu_bitdict[funame]
                     pick = fu.wr.rel[idx] & fu_active & wrflag
                     comb += wrpick.i[pi].eq(pick)
-                    comb += fu.go_wr_i[idx].eq(wrpick.o[pi])
+                    sync += fu.go_wr_i[idx].eq(wrpick.o[pi] & wrpick.en_o)
                     # connect regfile port to input
                     print ("reg connect widths",
                            regfile, regname, pi, funame,