From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 11 Jul 2020 16:34:07 +0000 (+0100)
Subject: sorting out bigendian/littleendian including in qemu
X-Git-Tag: div_pipeline~95
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9ecfd06b8498e5ac86eecf7b990053e3cb9ed903;p=soc.git

sorting out bigendian/littleendian including in qemu
qemu is a pain!
---

diff --git a/src/soc/config/endian.py b/src/soc/config/endian.py
new file mode 100644
index 00000000..eb6e0c3f
--- /dev/null
+++ b/src/soc/config/endian.py
@@ -0,0 +1,5 @@
+global bigendian
+bigendian = 0
+
+def set_endian_mode(mode):
+    bigendian = mode
diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index 3c3dcce5..aeeaa5d5 100644
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -250,7 +250,7 @@ class ISACaller:
                        initial_insns=None, respect_pc=False,
                        disassembly=None,
                        initial_pc=0,
-                       bigendian=True):
+                       bigendian=False):
 
         self.bigendian = bigendian
         self.halted = False
diff --git a/src/soc/decoder/power_decoder.py b/src/soc/decoder/power_decoder.py
index b7d1bc15..09cdd412 100644
--- a/src/soc/decoder/power_decoder.py
+++ b/src/soc/decoder/power_decoder.py
@@ -343,13 +343,13 @@ class TopPowerDecoder(PowerDecoder):
     def elaborate(self, platform):
         m = PowerDecoder.elaborate(self, platform)
         comb = m.d.comb
-        # raw opcode in, byte-reverse it
-        raw_be = self.raw_opcode_in
+        # raw opcode in assumed to be in LE order: byte-reverse it to get BE
+        raw_le = self.raw_opcode_in
         l = []
         for i in range(0, self.width, 8):
-            l.append(raw_be[i:i+8])
+            l.append(raw_le[i:i+8])
         l.reverse()
-        raw_le = Cat(*l)
+        raw_be = Cat(*l)
         comb += self.opcode_in.eq(Mux(self.bigendian, raw_be, raw_le))
 
         # add all signal from commonly-used fields
diff --git a/src/soc/fu/alu/test/test_pipe_caller.py b/src/soc/fu/alu/test/test_pipe_caller.py
index c5d250dd..6b3ae3f3 100644
--- a/src/soc/fu/alu/test/test_pipe_caller.py
+++ b/src/soc/fu/alu/test/test_pipe_caller.py
@@ -10,7 +10,7 @@ from soc.decoder.power_enums import (XER_bits, Function, InternalOp, CryIn)
 from soc.decoder.selectable_int import SelectableInt
 from soc.simulator.program import Program
 from soc.decoder.isa.all import ISA
-
+from soc.config.endian import bigendian
 
 from soc.fu.test.common import (TestCase, ALUHelpers)
 from soc.fu.alu.pipeline import ALUBasePipe
@@ -81,31 +81,31 @@ class ALUTestCase(FHDLTestCase):
         lst = [f"extsw 3, 1"]
         initial_regs = [0] * 32
         initial_regs[1] = 0xb6a1fc6c8576af91
-        self.run_tst_program(Program(lst), initial_regs)
+        self.run_tst_program(Program(lst, bigendian), initial_regs)
         lst = [f"subf 3, 1, 2"]
         initial_regs = [0] * 32
         initial_regs[1] = 0x3d7f3f7ca24bac7b
         initial_regs[2] = 0xf6b2ac5e13ee15c2
-        self.run_tst_program(Program(lst), initial_regs)
+        self.run_tst_program(Program(lst, bigendian), initial_regs)
         lst = [f"subf 3, 1, 2"]
         initial_regs = [0] * 32
         initial_regs[1] = 0x833652d96c7c0058
         initial_regs[2] = 0x1c27ecff8a086c1a
-        self.run_tst_program(Program(lst), initial_regs)
+        self.run_tst_program(Program(lst, bigendian), initial_regs)
         lst = [f"extsb 3, 1"]
         initial_regs = [0] * 32
         initial_regs[1] = 0x7f9497aaff900ea0
-        self.run_tst_program(Program(lst), initial_regs)
+        self.run_tst_program(Program(lst, bigendian), initial_regs)
         lst = [f"add. 3, 1, 2"]
         initial_regs = [0] * 32
         initial_regs[1] = 0xc523e996a8ff6215
         initial_regs[2] = 0xe1e5b9cc9864c4a8
-        self.run_tst_program(Program(lst), initial_regs)
+        self.run_tst_program(Program(lst, bigendian), initial_regs)
         lst = [f"add 3, 1, 2"]
         initial_regs = [0] * 32
         initial_regs[1] = 0x2e08ae202742baf8
         initial_regs[2] = 0x86c43ece9efe5baa
-        self.run_tst_program(Program(lst), initial_regs)
+        self.run_tst_program(Program(lst, bigendian), initial_regs)
 
     def test_rand(self):
         insns = ["add", "add.", "subf"]
@@ -115,7 +115,7 @@ class ALUTestCase(FHDLTestCase):
             initial_regs = [0] * 32
             initial_regs[1] = random.randint(0, (1<<64)-1)
             initial_regs[2] = random.randint(0, (1<<64)-1)
-            self.run_tst_program(Program(lst), initial_regs)
+            self.run_tst_program(Program(lst, bigendian), initial_regs)
 
     def test_rand_imm(self):
         insns = ["addi", "addis", "subfic"]
@@ -126,7 +126,7 @@ class ALUTestCase(FHDLTestCase):
             print(lst)
             initial_regs = [0] * 32
             initial_regs[1] = random.randint(0, (1<<64)-1)
-            self.run_tst_program(Program(lst), initial_regs)
+            self.run_tst_program(Program(lst, bigendian), initial_regs)
 
     def test_0_adde(self):
         lst = ["adde. 5, 6, 7"]
@@ -138,7 +138,7 @@ class ALUTestCase(FHDLTestCase):
             xer = SelectableInt(0, 64)
             xer[XER_bits['CA']] = 1
             initial_sprs[special_sprs['XER']] = xer
-            self.run_tst_program(Program(lst), initial_regs, initial_sprs)
+            self.run_tst_program(Program(lst, bigendian), initial_regs, initial_sprs)
 
     def test_cmp(self):
         lst = ["subf. 1, 6, 7",
@@ -146,7 +146,7 @@ class ALUTestCase(FHDLTestCase):
         initial_regs = [0] * 32
         initial_regs[6] = 0x10
         initial_regs[7] = 0x05
-        self.run_tst_program(Program(lst), initial_regs, {})
+        self.run_tst_program(Program(lst, bigendian), initial_regs, {})
 
     def test_extsb(self):
         insns = ["extsb", "extsh", "extsw"]
@@ -156,7 +156,7 @@ class ALUTestCase(FHDLTestCase):
             print(lst)
             initial_regs = [0] * 32
             initial_regs[1] = random.randint(0, (1<<64)-1)
-            self.run_tst_program(Program(lst), initial_regs)
+            self.run_tst_program(Program(lst, bigendian), initial_regs)
 
     def test_cmpeqb(self):
         lst = ["cmpeqb cr1, 1, 2"]
@@ -164,7 +164,7 @@ class ALUTestCase(FHDLTestCase):
             initial_regs = [0] * 32
             initial_regs[1] = i
             initial_regs[2] = 0x0001030507090b0f
-            self.run_tst_program(Program(lst), initial_regs, {})
+            self.run_tst_program(Program(lst, bigendian), initial_regs, {})
 
     def test_ilang(self):
         pspec = ALUPipeSpec(id_wid=2)
@@ -204,7 +204,8 @@ class TestRunner(FHDLTestCase):
                 program = test.program
                 self.subTest(test.name)
                 sim = ISA(pdecode2, test.regs, test.sprs, test.cr,
-                                test.mem, test.msr)
+                                test.mem, test.msr,
+                                bigendian=bigendian)
                 gen = program.generate_instructions()
                 instructions = list(zip(gen, program.assembly.splitlines()))
 
@@ -221,7 +222,7 @@ class TestRunner(FHDLTestCase):
                         print ("before: so/ov/32", so, ov, ov32)
 
                     # ask the decoder to decode this binary data (endian'd)
-                    yield pdecode2.dec.bigendian.eq(0)  # little / big?
+                    yield pdecode2.dec.bigendian.eq(bigendian)  # little / big?
                     yield instruction.eq(ins)          # raw binary instr.
                     yield Settle()
                     fn_unit = yield pdecode2.e.do.fn_unit
diff --git a/src/soc/fu/branch/test/test_pipe_caller.py b/src/soc/fu/branch/test/test_pipe_caller.py
index f9582323..947cff28 100644
--- a/src/soc/fu/branch/test/test_pipe_caller.py
+++ b/src/soc/fu/branch/test/test_pipe_caller.py
@@ -11,6 +11,7 @@ from soc.decoder.selectable_int import SelectableInt
 from soc.simulator.program import Program
 from soc.decoder.isa.all import ISA
 from soc.regfile.regfiles import FastRegs
+from soc.config.endian import bigendian
 
 from soc.fu.test.common import TestCase, ALUHelpers
 from soc.fu.branch.pipeline import BranchBasePipe
@@ -83,7 +84,7 @@ class BranchTestCase(FHDLTestCase):
             imm = random.randrange(-1<<23, (1<<23)-1) * 4
             lst = [f"{choice} {imm}"]
             initial_regs = [0] * 32
-            self.run_tst_program(Program(lst), initial_regs)
+            self.run_tst_program(Program(lst, bigendian), initial_regs)
 
     def test_bc_cr(self):
         for i in range(20):
@@ -93,7 +94,7 @@ class BranchTestCase(FHDLTestCase):
             cr = random.randrange(0, (1<<32)-1)
             lst = [f"bc {bo}, {bi}, {bc}"]
             initial_regs = [0] * 32
-            self.run_tst_program(Program(lst), initial_cr=cr)
+            self.run_tst_program(Program(lst, bigendian), initial_cr=cr)
 
     def test_bc_ctr(self):
         for i in range(20):
@@ -104,7 +105,7 @@ class BranchTestCase(FHDLTestCase):
             ctr = random.randint(0, (1<<32)-1)
             lst = [f"bc {bo}, {bi}, {bc}"]
             initial_sprs={9: SelectableInt(ctr, 64)}
-            self.run_tst_program(Program(lst),
+            self.run_tst_program(Program(lst, bigendian),
                                  initial_sprs=initial_sprs,
                                  initial_cr=cr)
 
@@ -124,7 +125,7 @@ class BranchTestCase(FHDLTestCase):
                 initial_sprs={9: SelectableInt(ctr, 64),
                               8: SelectableInt(lr, 64),
                               815: SelectableInt(tar, 64)}
-                self.run_tst_program(Program(lst),
+                self.run_tst_program(Program(lst, bigendian),
                                      initial_sprs=initial_sprs,
                                      initial_cr=cr)
 
@@ -166,7 +167,8 @@ class TestRunner(FHDLTestCase):
                 program = test.program
                 self.subTest(test.name)
                 simulator = ISA(pdecode2, test.regs, test.sprs, test.cr,
-                                test.mem, test.msr)
+                                test.mem, test.msr,
+                                bigendian=bigendian)
                 initial_cia = 0x2000
                 simulator.set_pc(initial_cia)
                 gen = program.generate_instructions()
@@ -181,7 +183,7 @@ class TestRunner(FHDLTestCase):
                     print(code)
 
                     # ask the decoder to decode this binary data (endian'd)
-                    yield pdecode2.dec.bigendian.eq(0)  # little / big?
+                    yield pdecode2.dec.bigendian.eq(bigendian)  # little / big?
                     yield instruction.eq(ins)          # raw binary instr.
                     # note, here, the op will need further decoding in order
                     # to set the correct SPRs on SPR1/2/3.  op_bc* require
diff --git a/src/soc/fu/compunits/test/test_compunit.py b/src/soc/fu/compunits/test/test_compunit.py
index cffa0316..7a73cb83 100644
--- a/src/soc/fu/compunits/test/test_compunit.py
+++ b/src/soc/fu/compunits/test/test_compunit.py
@@ -11,6 +11,7 @@ from soc.decoder.isa.all import ISA
 from soc.experiment.compalu_multi import find_ok # hack
 from soc.config.test.test_loadstore import TestMemPspec
 
+
 def set_cu_input(cu, idx, data):
     rdop = cu.get_in_name(idx)
     yield cu.src_i[idx].eq(data)
@@ -147,12 +148,13 @@ def check_sim_memory(dut, l0, sim, code):
                                  expected_mem, actual_mem))
 
 class TestRunner(FHDLTestCase):
-    def __init__(self, test_data, fukls, iodef, funit):
+    def __init__(self, test_data, fukls, iodef, funit, bigendian):
         super().__init__("run_all")
         self.test_data = test_data
         self.fukls = fukls
         self.iodef = iodef
         self.funit = funit
+        self.bigendian = bigendian
 
     def run_all(self):
         m = Module()
@@ -202,7 +204,7 @@ class TestRunner(FHDLTestCase):
                           test.msr,
                           initial_insns=gen, respect_pc=False,
                           disassembly=insncode,
-                          bigendian=False)
+                          bigendian=self.bigendian)
 
                 # initialise memory
                 if self.funit == Function.LDST:
@@ -219,7 +221,7 @@ class TestRunner(FHDLTestCase):
                     print(index, code)
 
                     # ask the decoder to decode this binary data (endian'd)
-                    yield pdecode2.dec.bigendian.eq(0)  # little / big?
+                    yield pdecode2.dec.bigendian.eq(self.bigendian)  # le / be?
                     yield instruction.eq(ins)          # raw binary instr.
                     yield Settle()
                     fn_unit = yield pdecode2.e.do.fn_unit
diff --git a/src/soc/fu/compunits/test/test_cr_compunit.py b/src/soc/fu/compunits/test/test_cr_compunit.py
index 9d05d3f7..50e9d133 100644
--- a/src/soc/fu/compunits/test/test_cr_compunit.py
+++ b/src/soc/fu/compunits/test/test_cr_compunit.py
@@ -7,12 +7,13 @@ from soc.fu.cr.test.test_pipe_caller import CRTestCase
 
 from soc.fu.compunits.compunits import CRFunctionUnit
 from soc.fu.compunits.test.test_compunit import TestRunner
+from soc.config.endian import bigendian
 
 
 class CRTestRunner(TestRunner):
     def __init__(self, test_data):
         super().__init__(test_data, CRFunctionUnit, self,
-                         Function.CR)
+                         Function.CR, bigendian)
 
     def get_cu_inputs(self, dec2, sim):
         """naming (res) must conform to CRFunctionUnit input regspec
diff --git a/src/soc/fu/compunits/test/test_logical_compunit.py b/src/soc/fu/compunits/test/test_logical_compunit.py
index 439901a5..877f14c5 100644
--- a/src/soc/fu/compunits/test/test_logical_compunit.py
+++ b/src/soc/fu/compunits/test/test_logical_compunit.py
@@ -1,17 +1,19 @@
 import unittest
 from soc.decoder.power_enums import (XER_bits, Function)
 
-from soc.fu.logical.test.test_pipe_caller import LogicalTestCase, get_cu_inputs
+from soc.fu.logical.test.test_pipe_caller import (LogicalTestCase,
+                                                  get_cu_inputs)
 
 from soc.fu.compunits.compunits import LogicalFunctionUnit
 from soc.fu.compunits.test.test_compunit import TestRunner
 from soc.fu.test.common import ALUHelpers
+from soc.config.endian import bigendian
 
 
 class LogicalTestRunner(TestRunner):
     def __init__(self, test_data):
         super().__init__(test_data, LogicalFunctionUnit, self,
-                         Function.LOGICAL)
+                         Function.LOGICAL, bigendian)
 
     def get_cu_inputs(self, dec2, sim):
         """naming (res) must conform to LogicalFunctionUnit input regspec
diff --git a/src/soc/fu/cr/test/test_pipe_caller.py b/src/soc/fu/cr/test/test_pipe_caller.py
index e6e38bca..27ea17b7 100644
--- a/src/soc/fu/cr/test/test_pipe_caller.py
+++ b/src/soc/fu/cr/test/test_pipe_caller.py
@@ -10,7 +10,7 @@ from soc.decoder.power_enums import (XER_bits, Function)
 from soc.decoder.selectable_int import SelectableInt
 from soc.simulator.program import Program
 from soc.decoder.isa.all import ISA
-
+from soc.config.endian import bigendian
 
 from soc.fu.test.common import TestCase, ALUHelpers
 from soc.fu.cr.pipeline import CRBasePipe
@@ -60,13 +60,13 @@ class CRTestCase(FHDLTestCase):
             bt = random.randint(0, 31)
             lst = [f"{choice} {ba}, {bb}, {bt}"]
             cr = random.randint(0, (1<<32)-1)
-            self.run_tst_program(Program(lst), initial_cr=cr)
+            self.run_tst_program(Program(lst, bigendian), initial_cr=cr)
 
     def test_crand(self):
         for i in range(20):
             lst = ["crand 0, 11, 13"]
             cr = random.randint(0, (1<<32)-1)
-            self.run_tst_program(Program(lst), initial_cr=cr)
+            self.run_tst_program(Program(lst, bigendian), initial_cr=cr)
 
     def test_1_mcrf(self):
         for i in range(20):
@@ -74,13 +74,13 @@ class CRTestCase(FHDLTestCase):
             dst = random.randint(0, 7)
             lst = [f"mcrf {src}, {dst}"]
             cr = random.randint(0, (1<<32)-1)
-        self.run_tst_program(Program(lst), initial_cr=cr)
+        self.run_tst_program(Program(lst, bigendian), initial_cr=cr)
 
     def test_0_mcrf(self):
         for i in range(8):
             lst = [f"mcrf 5, {i}"]
             cr = 0xfeff0001
-            self.run_tst_program(Program(lst), initial_cr=cr)
+            self.run_tst_program(Program(lst, bigendian), initial_cr=cr)
 
     def test_mtcrf(self):
         for i in range(20):
@@ -89,7 +89,7 @@ class CRTestCase(FHDLTestCase):
             cr = random.randint(0, (1<<32)-1)
             initial_regs = [0] * 32
             initial_regs[2] = random.randint(0, (1<<32)-1)
-            self.run_tst_program(Program(lst), initial_regs=initial_regs,
+            self.run_tst_program(Program(lst, bigendian), initial_regs=initial_regs,
                                  initial_cr=cr)
     def test_mtocrf(self):
         for i in range(20):
@@ -98,21 +98,21 @@ class CRTestCase(FHDLTestCase):
             cr = random.randint(0, (1<<32)-1)
             initial_regs = [0] * 32
             initial_regs[2] = random.randint(0, (1<<32)-1)
-            self.run_tst_program(Program(lst), initial_regs=initial_regs,
+            self.run_tst_program(Program(lst, bigendian), initial_regs=initial_regs,
                                  initial_cr=cr)
 
     def test_mfcr(self):
         for i in range(5):
             lst = ["mfcr 2"]
             cr = random.randint(0, (1<<32)-1)
-            self.run_tst_program(Program(lst), initial_cr=cr)
+            self.run_tst_program(Program(lst, bigendian), initial_cr=cr)
 
     def test_mfocrf(self):
         for i in range(20):
             mask = 1<<random.randint(0, 7)
             lst = [f"mfocrf 2, {mask}"]
             cr = random.randint(0, (1<<32)-1)
-            self.run_tst_program(Program(lst), initial_cr=cr)
+            self.run_tst_program(Program(lst, bigendian), initial_cr=cr)
 
     def test_isel(self):
         for i in range(20):
@@ -124,7 +124,7 @@ class CRTestCase(FHDLTestCase):
             initial_regs[3] = random.randint(0, (1<<64)-1)
             #initial_regs[2] = i*2
             #initial_regs[3] = i*2+1
-            self.run_tst_program(Program(lst),
+            self.run_tst_program(Program(lst, bigendian),
                                  initial_regs=initial_regs, initial_cr=cr)
 
     def test_setb(self):
@@ -132,9 +132,7 @@ class CRTestCase(FHDLTestCase):
             bfa = random.randint(0, 7)
             lst = [f"setb 1, {bfa}"]
             cr = random.randint(0, (1<<32)-1)
-            self.run_tst_program(Program(lst), initial_cr=cr)
-
-            
+            self.run_tst_program(Program(lst, bigendian), initial_cr=cr)
 
     def test_ilang(self):
         pspec = CRPipeSpec(id_wid=2)
@@ -249,7 +247,8 @@ class TestRunner(FHDLTestCase):
                 program = test.program
                 self.subTest(test.name)
                 sim = ISA(pdecode2, test.regs, test.sprs, test.cr, test.mem,
-                          test.msr)
+                          test.msr,
+                          bigendian=bigendian)
                 gen = program.generate_instructions()
                 instructions = list(zip(gen, program.assembly.splitlines()))
 
@@ -261,7 +260,7 @@ class TestRunner(FHDLTestCase):
                     print(code)
 
                     # ask the decoder to decode this binary data (endian'd)
-                    yield pdecode2.dec.bigendian.eq(0)  # little / big?
+                    yield pdecode2.dec.bigendian.eq(bigendian)  # little / big?
                     yield instruction.eq(ins)          # raw binary instr.
                     yield Settle()
                     yield from self.set_inputs(alu, pdecode2, sim)
diff --git a/src/soc/fu/div/test/test_pipe_caller.py b/src/soc/fu/div/test/test_pipe_caller.py
index 02f9f996..65aa0801 100644
--- a/src/soc/fu/div/test/test_pipe_caller.py
+++ b/src/soc/fu/div/test/test_pipe_caller.py
@@ -10,7 +10,7 @@ from soc.decoder.power_enums import (XER_bits, Function, InternalOp, CryIn)
 from soc.decoder.selectable_int import SelectableInt
 from soc.simulator.program import Program
 from soc.decoder.isa.all import ISA
-
+from soc.config.endian import bigendian
 
 from soc.fu.test.common import (TestCase, ALUHelpers)
 from soc.fu.div.pipeline import DIVBasePipe
@@ -78,43 +78,43 @@ class DIVTestCase(FHDLTestCase):
         tc = TestCase(prog, self.test_name, initial_regs, initial_sprs)
         self.test_data.append(tc)
 
-    def test_0_regression(self):
+    def tst_0_regression(self):
         for i in range(40):
             lst = ["divwo 3, 1, 2"]
             initial_regs = [0] * 32
             initial_regs[1] = 0xbc716835f32ac00c
             initial_regs[2] = 0xcdf69a7f7042db66
-            self.run_tst_program(Program(lst), initial_regs)
+            self.run_tst_program(Program(lst, bigendian), initial_regs)
 
-    def test_1_regression(self):
+    def tst_1_regression(self):
         lst = ["divwo 3, 1, 2"]
         initial_regs = [0] * 32
         initial_regs[1] = 0x10000000000000000-4
         initial_regs[2] = 0x10000000000000000-2
-        self.run_tst_program(Program(lst), initial_regs)
+        self.run_tst_program(Program(lst, bigendian), initial_regs)
 
-    def test_2_regression(self):
+    def tst_2_regression(self):
         lst = ["divwo 3, 1, 2"]
         initial_regs = [0] * 32
         initial_regs[1] = 0xffffffffffff9321
         initial_regs[2] = 0xffffffffffff7012
-        self.run_tst_program(Program(lst), initial_regs)
+        self.run_tst_program(Program(lst, bigendian), initial_regs)
 
-    def test_3_regression(self):
+    def tst_3_regression(self):
         lst = ["divwo. 3, 1, 2"]
         initial_regs = [0] * 32
         initial_regs[1] = 0x1b8e32f2458746af
         initial_regs[2] = 0x6b8aee2ccf7d62e9
-        self.run_tst_program(Program(lst), initial_regs)
+        self.run_tst_program(Program(lst, bigendian), initial_regs)
 
-    def test_4_regression(self):
+    def tst_4_regression(self):
         lst = ["divw 3, 1, 2"]
         initial_regs = [0] * 32
         initial_regs[1] = 0x1c4e6c2f3aa4a05c
         initial_regs[2] = 0xe730c2eed6cc8dd7
-        self.run_tst_program(Program(lst), initial_regs)
+        self.run_tst_program(Program(lst, bigendian), initial_regs)
 
-    def test_5_regression(self):
+    def tst_5_regression(self):
         lst = ["divw 3, 1, 2",
                "divwo. 6, 4, 5"]
         initial_regs = [0] * 32
@@ -122,9 +122,9 @@ class DIVTestCase(FHDLTestCase):
         initial_regs[2] = 0xe730c2eed6cc8dd7
         initial_regs[4] = 0x1b8e32f2458746af
         initial_regs[5] = 0x6b8aee2ccf7d62e9
-        self.run_tst_program(Program(lst), initial_regs)
+        self.run_tst_program(Program(lst, bigendian), initial_regs)
 
-    def test_6_regression(self):
+    def tst_6_regression(self):
         # CR0 not getting set properly for this one
         # turns out that overflow is not set correctly in
         # fu/div/output_stage.py calc_overflow
@@ -133,7 +133,7 @@ class DIVTestCase(FHDLTestCase):
         initial_regs = [0] * 32
         initial_regs[1] = 0x61c1cc3b80f2a6af
         initial_regs[2] = 0x9dc66a7622c32bc0
-        self.run_tst_program(Program(lst), initial_regs)
+        self.run_tst_program(Program(lst, bigendian), initial_regs)
 
     def test_7_regression(self):
         # https://bugs.libre-soc.org/show_bug.cgi?id=425
@@ -141,30 +141,30 @@ class DIVTestCase(FHDLTestCase):
         initial_regs = [0] * 32
         initial_regs[1] = 0xf1791627e05e8096
         initial_regs[2] = 0xffc868bf4573da0b
-        self.run_tst_program(Program(lst), initial_regs)
+        self.run_tst_program(Program(lst, bigendian), initial_regs)
 
-    def test_divw_by_zero_1(self):
+    def tst_divw_by_zero_1(self):
         lst = ["divw. 3, 1, 2"]
         initial_regs = [0] * 32
         initial_regs[1] = 0x1
         initial_regs[2] = 0x0
-        self.run_tst_program(Program(lst), initial_regs)
+        self.run_tst_program(Program(lst, bigendian), initial_regs)
 
-    def test_divw_overflow2(self):
+    def tst_divw_overflow2(self):
         lst = ["divw. 3, 1, 2"]
         initial_regs = [0] * 32
         initial_regs[1] = 0x80000000
         initial_regs[2] = 0xffffffffffffffff # top bits don't seem to matter
-        self.run_tst_program(Program(lst), initial_regs)
+        self.run_tst_program(Program(lst, bigendian), initial_regs)
 
-    def test_divw_overflow3(self):
+    def tst_divw_overflow3(self):
         lst = ["divw. 3, 1, 2"]
         initial_regs = [0] * 32
         initial_regs[1] = 0x80000000
         initial_regs[2] = 0xffffffff
-        self.run_tst_program(Program(lst), initial_regs)
+        self.run_tst_program(Program(lst, bigendian), initial_regs)
 
-    def test_rand_divw(self):
+    def tst_rand_divw(self):
         insns = ["divw", "divw.", "divwo", "divwo."]
         for i in range(40):
             choice = random.choice(insns)
@@ -172,23 +172,23 @@ class DIVTestCase(FHDLTestCase):
             initial_regs = [0] * 32
             initial_regs[1] = log_rand(32)
             initial_regs[2] = log_rand(32)
-            self.run_tst_program(Program(lst), initial_regs)
+            self.run_tst_program(Program(lst, bigendian), initial_regs)
 
-    def test_divwuo_regression_1(self):
+    def tst_divwuo_regression_1(self):
         lst = ["divwuo. 3, 1, 2"]
         initial_regs = [0] * 32
         initial_regs[1] = 0x7591a398c4e32b68
         initial_regs[2] = 0x48674ab432867d69
-        self.run_tst_program(Program(lst), initial_regs)
+        self.run_tst_program(Program(lst, bigendian), initial_regs)
 
-    def test_divwuo_1(self):
+    def tst_divwuo_1(self):
         lst = ["divwuo. 3, 1, 2"]
         initial_regs = [0] * 32
         initial_regs[1] = 0x50
         initial_regs[2] = 0x2
-        self.run_tst_program(Program(lst), initial_regs)
+        self.run_tst_program(Program(lst, bigendian), initial_regs)
 
-    def test_rand_divwu(self):
+    def tst_rand_divwu(self):
         insns = ["divwu", "divwu.", "divwuo", "divwuo."]
         for i in range(40):
             choice = random.choice(insns)
@@ -196,9 +196,9 @@ class DIVTestCase(FHDLTestCase):
             initial_regs = [0] * 32
             initial_regs[1] = log_rand(32)
             initial_regs[2] = log_rand(32)
-            self.run_tst_program(Program(lst), initial_regs)
+            self.run_tst_program(Program(lst, bigendian), initial_regs)
 
-    def test_ilang(self):
+    def tst_ilang(self):
         pspec = DIVPipeSpec(id_wid=2)
         alu = DIVBasePipe(pspec)
         vl = rtlil.convert(alu, ports=alu.ports())
@@ -235,7 +235,8 @@ class TestRunner(FHDLTestCase):
                 program = test.program
                 self.subTest(test.name)
                 sim = ISA(pdecode2, test.regs, test.sprs, test.cr,
-                                test.mem, test.msr)
+                                test.mem, test.msr,
+                                bigendian=bigendian)
                 gen = program.generate_instructions()
                 instructions = list(zip(gen, program.assembly.splitlines()))
                 yield Settle()
@@ -253,7 +254,7 @@ class TestRunner(FHDLTestCase):
                         print ("before: so/ov/32", so, ov, ov32)
 
                     # ask the decoder to decode this binary data (endian'd)
-                    yield pdecode2.dec.bigendian.eq(0)  # little / big?
+                    yield pdecode2.dec.bigendian.eq(bigendian)  # little / big?
                     yield instruction.eq(ins)          # raw binary instr.
                     yield Settle()
                     fn_unit = yield pdecode2.e.do.fn_unit
diff --git a/src/soc/fu/logical/test/test_pipe_caller.py b/src/soc/fu/logical/test/test_pipe_caller.py
index 03c81949..d75ba813 100644
--- a/src/soc/fu/logical/test/test_pipe_caller.py
+++ b/src/soc/fu/logical/test/test_pipe_caller.py
@@ -10,6 +10,8 @@ from soc.decoder.power_enums import (XER_bits, Function)
 from soc.decoder.selectable_int import SelectableInt
 from soc.simulator.program import Program
 from soc.decoder.isa.all import ISA
+from soc.config.endian import bigendian
+
 
 from soc.fu.test.common import TestCase, ALUHelpers
 from soc.fu.logical.pipeline import LogicalBasePipe
@@ -75,7 +77,7 @@ class LogicalTestCase(FHDLTestCase):
             initial_regs = [0] * 32
             initial_regs[1] = random.randint(0, (1 << 64)-1)
             initial_regs[2] = random.randint(0, (1 << 64)-1)
-            self.run_tst_program(Program(lst), initial_regs)
+            self.run_tst_program(Program(lst, bigendian), initial_regs)
 
     def test_rand_imm_logical(self):
         insns = ["andi.", "andis.", "ori", "oris", "xori", "xoris"]
@@ -86,7 +88,7 @@ class LogicalTestCase(FHDLTestCase):
             print(lst)
             initial_regs = [0] * 32
             initial_regs[1] = random.randint(0, (1 << 64)-1)
-            self.run_tst_program(Program(lst), initial_regs)
+            self.run_tst_program(Program(lst, bigendian), initial_regs)
 
     def test_cntz(self):
         insns = ["cntlzd", "cnttzd", "cntlzw", "cnttzw"]
@@ -96,7 +98,7 @@ class LogicalTestCase(FHDLTestCase):
             print(lst)
             initial_regs = [0] * 32
             initial_regs[1] = random.randint(0, (1 << 64)-1)
-            self.run_tst_program(Program(lst), initial_regs)
+            self.run_tst_program(Program(lst, bigendian), initial_regs)
 
     def test_parity(self):
         insns = ["prtyw", "prtyd"]
@@ -106,7 +108,7 @@ class LogicalTestCase(FHDLTestCase):
             print(lst)
             initial_regs = [0] * 32
             initial_regs[1] = random.randint(0, (1 << 64)-1)
-            self.run_tst_program(Program(lst), initial_regs)
+            self.run_tst_program(Program(lst, bigendian), initial_regs)
 
     def test_popcnt(self):
         insns = ["popcntb", "popcntw", "popcntd"]
@@ -116,7 +118,7 @@ class LogicalTestCase(FHDLTestCase):
             print(lst)
             initial_regs = [0] * 32
             initial_regs[1] = random.randint(0, (1 << 64)-1)
-            self.run_tst_program(Program(lst), initial_regs)
+            self.run_tst_program(Program(lst, bigendian), initial_regs)
 
     def test_popcnt_edge(self):
         insns = ["popcntb", "popcntw", "popcntd"]
@@ -124,14 +126,14 @@ class LogicalTestCase(FHDLTestCase):
             lst = [f"{choice} 3, 1"]
             initial_regs = [0] * 32
             initial_regs[1] = -1
-            self.run_tst_program(Program(lst), initial_regs)
+            self.run_tst_program(Program(lst, bigendian), initial_regs)
 
     def test_cmpb(self):
         lst = ["cmpb 3, 1, 2"]
         initial_regs = [0] * 32
         initial_regs[1] = 0xdeadbeefcafec0de
         initial_regs[2] = 0xd0adb0000afec1de
-        self.run_tst_program(Program(lst), initial_regs)
+        self.run_tst_program(Program(lst, bigendian), initial_regs)
 
     def test_bpermd(self):
         lst = ["bpermd 3, 1, 2"]
@@ -139,7 +141,7 @@ class LogicalTestCase(FHDLTestCase):
             initial_regs = [0] * 32
             initial_regs[1] = 1<<random.randint(0,63)
             initial_regs[2] = 0xdeadbeefcafec0de
-            self.run_tst_program(Program(lst), initial_regs)
+            self.run_tst_program(Program(lst, bigendian), initial_regs)
 
     def test_ilang(self):
         pspec = LogicalPipeSpec(id_wid=2)
@@ -180,7 +182,8 @@ class TestRunner(FHDLTestCase):
                 program = test.program
                 self.subTest(test.name)
                 simulator = ISA(pdecode2, test.regs, test.sprs, test.cr,
-                                test.mem, test.msr)
+                                test.mem, test.msr,
+                                bigendian=bigendian)
                 gen = program.generate_instructions()
                 instructions = list(zip(gen, program.assembly.splitlines()))
 
@@ -192,7 +195,7 @@ class TestRunner(FHDLTestCase):
                     print(code)
 
                     # ask the decoder to decode this binary data (endian'd)
-                    yield pdecode2.dec.bigendian.eq(0)  # little / big?
+                    yield pdecode2.dec.bigendian.eq(bigendian)  # little / big?
                     yield instruction.eq(ins)          # raw binary instr.
                     yield Settle()
                     fn_unit = yield pdecode2.e.do.fn_unit
diff --git a/src/soc/fu/mul/test/test_pipe_caller.py b/src/soc/fu/mul/test/test_pipe_caller.py
index fe668674..b85c0e04 100644
--- a/src/soc/fu/mul/test/test_pipe_caller.py
+++ b/src/soc/fu/mul/test/test_pipe_caller.py
@@ -10,7 +10,7 @@ from soc.decoder.power_enums import (XER_bits, Function, InternalOp, CryIn)
 from soc.decoder.selectable_int import SelectableInt
 from soc.simulator.program import Program
 from soc.decoder.isa.all import ISA
-
+from soc.config.endian import bigendian
 
 from soc.fu.test.common import (TestCase, ALUHelpers)
 from soc.fu.mul.pipeline import MulBasePipe
@@ -83,21 +83,21 @@ class MulTestCase(FHDLTestCase):
         #initial_regs[2] = 0xffffffffffffffff
         initial_regs[1] = 0x2ffffffff
         initial_regs[2] = 0x2
-        self.run_tst_program(Program(lst), initial_regs)
+        self.run_tst_program(Program(lst, bigendian), initial_regs)
 
     def test_1_mullwo_(self):
         lst = [f"mullwo. 3, 1, 2"]
         initial_regs = [0] * 32
         initial_regs[1] = 0x3b34b06f
         initial_regs[2] = 0xfdeba998
-        self.run_tst_program(Program(lst), initial_regs)
+        self.run_tst_program(Program(lst, bigendian), initial_regs)
 
     def test_2_mullwo(self):
         lst = [f"mullwo 3, 1, 2"]
         initial_regs = [0] * 32
         initial_regs[1] = 0xffffffffffffa988 # -5678
         initial_regs[2] = 0xffffffffffffedcc # -1234
-        self.run_tst_program(Program(lst), initial_regs)
+        self.run_tst_program(Program(lst, bigendian), initial_regs)
 
     def test_3_mullw(self):
         lst = ["mullw 3, 1, 2",
@@ -105,7 +105,7 @@ class MulTestCase(FHDLTestCase):
         initial_regs = [0] * 32
         initial_regs[1] = 0x6
         initial_regs[2] = 0xe
-        self.run_tst_program(Program(lst), initial_regs)
+        self.run_tst_program(Program(lst, bigendian), initial_regs)
 
     def test_4_mullw_rand(self):
         for i in range(40):
@@ -113,7 +113,7 @@ class MulTestCase(FHDLTestCase):
             initial_regs = [0] * 32
             initial_regs[1] = random.randint(0, (1<<64)-1)
             initial_regs[2] = random.randint(0, (1<<64)-1)
-            self.run_tst_program(Program(lst), initial_regs)
+            self.run_tst_program(Program(lst, bigendian), initial_regs)
 
     def test_4_mullw_nonrand(self):
         for i in range(40):
@@ -121,7 +121,7 @@ class MulTestCase(FHDLTestCase):
             initial_regs = [0] * 32
             initial_regs[1] = i+1
             initial_regs[2] = i+20
-            self.run_tst_program(Program(lst), initial_regs)
+            self.run_tst_program(Program(lst, bigendian), initial_regs)
 
     def test_mulhw__regression_1(self):
         lst = ["mulhw. 3, 1, 2"
@@ -129,7 +129,7 @@ class MulTestCase(FHDLTestCase):
         initial_regs = [0] * 32
         initial_regs[1] = 0x7745b36eca6646fa
         initial_regs[2] = 0x47dfba3a63834ba2
-        self.run_tst_program(Program(lst), initial_regs)
+        self.run_tst_program(Program(lst, bigendian), initial_regs)
 
     def test_4_mullw_rand(self):
         for i in range(40):
@@ -137,7 +137,7 @@ class MulTestCase(FHDLTestCase):
             initial_regs = [0] * 32
             initial_regs[1] = random.randint(0, (1<<64)-1)
             initial_regs[2] = random.randint(0, (1<<64)-1)
-            self.run_tst_program(Program(lst), initial_regs)
+            self.run_tst_program(Program(lst, bigendian), initial_regs)
 
     def test_rand_mul_lh(self):
         insns = ["mulhw", "mulhw.", "mulhwu", "mulhwu."]
@@ -147,7 +147,7 @@ class MulTestCase(FHDLTestCase):
             initial_regs = [0] * 32
             initial_regs[1] = random.randint(0, (1<<64)-1)
             initial_regs[2] = random.randint(0, (1<<64)-1)
-            self.run_tst_program(Program(lst), initial_regs)
+            self.run_tst_program(Program(lst, bigendian), initial_regs)
 
     def test_rand_mullw(self):
         insns = ["mullw", "mullw.", "mullwo", "mullwo."]
@@ -157,7 +157,7 @@ class MulTestCase(FHDLTestCase):
             initial_regs = [0] * 32
             initial_regs[1] = random.randint(0, (1<<64)-1)
             initial_regs[2] = random.randint(0, (1<<64)-1)
-            self.run_tst_program(Program(lst), initial_regs)
+            self.run_tst_program(Program(lst, bigendian), initial_regs)
 
     def test_rand_mulld(self):
         insns = ["mulld", "mulld.", "mulldo", "mulldo."]
@@ -167,7 +167,7 @@ class MulTestCase(FHDLTestCase):
             initial_regs = [0] * 32
             initial_regs[1] = random.randint(0, (1<<64)-1)
             initial_regs[2] = random.randint(0, (1<<64)-1)
-            self.run_tst_program(Program(lst), initial_regs)
+            self.run_tst_program(Program(lst, bigendian), initial_regs)
 
     def test_rand_mulhd(self):
         insns = ["mulhd", "mulhd."]
@@ -177,7 +177,7 @@ class MulTestCase(FHDLTestCase):
             initial_regs = [0] * 32
             initial_regs[1] = random.randint(0, (1<<64)-1)
             initial_regs[2] = random.randint(0, (1<<64)-1)
-            self.run_tst_program(Program(lst), initial_regs)
+            self.run_tst_program(Program(lst, bigendian), initial_regs)
 
     def test_ilang(self):
         pspec = MulPipeSpec(id_wid=2)
@@ -216,7 +216,8 @@ class TestRunner(FHDLTestCase):
                 program = test.program
                 self.subTest(test.name)
                 sim = ISA(pdecode2, test.regs, test.sprs, test.cr,
-                                test.mem, test.msr)
+                                test.mem, test.msr,
+                                bigendian=bigendian)
                 gen = program.generate_instructions()
                 instructions = list(zip(gen, program.assembly.splitlines()))
                 yield Settle()
@@ -234,7 +235,7 @@ class TestRunner(FHDLTestCase):
                         print ("before: so/ov/32", so, ov, ov32)
 
                     # ask the decoder to decode this binary data (endian'd)
-                    yield pdecode2.dec.bigendian.eq(0)  # little / big?
+                    yield pdecode2.dec.bigendian.eq(bigendian)  # little / big?
                     yield instruction.eq(ins)          # raw binary instr.
                     yield Settle()
                     fn_unit = yield pdecode2.e.do.fn_unit
diff --git a/src/soc/fu/shift_rot/test/test_pipe_caller.py b/src/soc/fu/shift_rot/test/test_pipe_caller.py
index 62f0d5a5..263de991 100644
--- a/src/soc/fu/shift_rot/test/test_pipe_caller.py
+++ b/src/soc/fu/shift_rot/test/test_pipe_caller.py
@@ -10,7 +10,7 @@ from soc.decoder.power_enums import (XER_bits, Function, CryIn)
 from soc.decoder.selectable_int import SelectableInt
 from soc.simulator.program import Program
 from soc.decoder.isa.all import ISA
-
+from soc.config.endian import bigendian
 
 from soc.fu.test.common import TestCase, ALUHelpers
 from soc.fu.shift_rot.pipeline import ShiftRotBasePipe
@@ -84,7 +84,7 @@ class ShiftRotTestCase(FHDLTestCase):
             initial_regs[1] = random.randint(0, (1<<64)-1)
             initial_regs[2] = random.randint(0, 63)
             print(initial_regs[1], initial_regs[2])
-            self.run_tst_program(Program(lst), initial_regs)
+            self.run_tst_program(Program(lst, bigendian), initial_regs)
 
     def test_shift_arith(self):
         lst = ["sraw 3, 1, 2"]
@@ -92,7 +92,7 @@ class ShiftRotTestCase(FHDLTestCase):
         initial_regs[1] = random.randint(0, (1<<64)-1)
         initial_regs[2] = random.randint(0, 63)
         print(initial_regs[1], initial_regs[2])
-        self.run_tst_program(Program(lst), initial_regs)
+        self.run_tst_program(Program(lst, bigendian), initial_regs)
 
     def test_shift_once(self):
         lst = ["slw 3, 1, 4",
@@ -101,7 +101,7 @@ class ShiftRotTestCase(FHDLTestCase):
         initial_regs[1] = 0x80000000
         initial_regs[2] = 0x40
         initial_regs[4] = 0x00
-        self.run_tst_program(Program(lst), initial_regs)
+        self.run_tst_program(Program(lst, bigendian), initial_regs)
 
     def test_rlwinm(self):
         for i in range(10):
@@ -113,33 +113,33 @@ class ShiftRotTestCase(FHDLTestCase):
                    ]
             initial_regs = [0] * 32
             initial_regs[1] = random.randint(0, (1<<64)-1)
-            self.run_tst_program(Program(lst), initial_regs)
+            self.run_tst_program(Program(lst, bigendian), initial_regs)
 
     def test_rlwimi(self):
         lst = ["rlwimi 3, 1, 5, 20, 6"]
         initial_regs = [0] * 32
         initial_regs[1] = 0xdeadbeef
         initial_regs[3] = 0x12345678
-        self.run_tst_program(Program(lst), initial_regs)
+        self.run_tst_program(Program(lst, bigendian), initial_regs)
 
     def test_rlwnm(self):
         lst = ["rlwnm 3, 1, 2, 20, 6"]
         initial_regs = [0] * 32
         initial_regs[1] = random.randint(0, (1<<64)-1)
         initial_regs[2] = random.randint(0, 63)
-        self.run_tst_program(Program(lst), initial_regs)
+        self.run_tst_program(Program(lst, bigendian), initial_regs)
 
     def test_rldicl(self):
         lst = ["rldicl 3, 1, 5, 20"]
         initial_regs = [0] * 32
         initial_regs[1] = random.randint(0, (1<<64)-1)
-        self.run_tst_program(Program(lst), initial_regs)
+        self.run_tst_program(Program(lst, bigendian), initial_regs)
 
     def test_rldicr(self):
         lst = ["rldicr 3, 1, 5, 20"]
         initial_regs = [0] * 32
         initial_regs[1] = random.randint(0, (1<<64)-1)
-        self.run_tst_program(Program(lst), initial_regs)
+        self.run_tst_program(Program(lst, bigendian), initial_regs)
 
     def test_rlc(self):
         insns = ["rldic", "rldicl", "rldicr"]
@@ -150,7 +150,7 @@ class ShiftRotTestCase(FHDLTestCase):
             lst = [f"{choice} 3, 1, {sh}, {m}"]
             initial_regs = [0] * 32
             initial_regs[1] = random.randint(0, (1<<64)-1)
-            self.run_tst_program(Program(lst), initial_regs)
+            self.run_tst_program(Program(lst, bigendian), initial_regs)
 
     def test_ilang(self):
         pspec = ShiftRotPipeSpec(id_wid=2)
@@ -190,7 +190,8 @@ class TestRunner(FHDLTestCase):
                 program = test.program
                 self.subTest(test.name)
                 simulator = ISA(pdecode2, test.regs, test.sprs, test.cr,
-                                test.mem, test.msr)
+                                test.mem, test.msr,
+                                bigendian=bigendian)
                 gen = program.generate_instructions()
                 instructions = list(zip(gen, program.assembly.splitlines()))
 
@@ -202,7 +203,7 @@ class TestRunner(FHDLTestCase):
                     print(code)
 
                     # ask the decoder to decode this binary data (endian'd)
-                    yield pdecode2.dec.bigendian.eq(0)  # little / big?
+                    yield pdecode2.dec.bigendian.eq(bigendian)  # little / big?
                     yield instruction.eq(ins)          # raw binary instr.
                     yield Settle()
                     fn_unit = yield pdecode2.e.do.fn_unit
diff --git a/src/soc/fu/spr/test/test_pipe_caller.py b/src/soc/fu/spr/test/test_pipe_caller.py
index ce412bdf..d879d439 100644
--- a/src/soc/fu/spr/test/test_pipe_caller.py
+++ b/src/soc/fu/spr/test/test_pipe_caller.py
@@ -10,7 +10,7 @@ from soc.decoder.power_enums import (XER_bits, Function, InternalOp, CryIn)
 from soc.decoder.selectable_int import SelectableInt
 from soc.simulator.program import Program
 from soc.decoder.isa.all import ISA
-
+from soc.config.endian import bigendian
 
 from soc.fu.test.common import (TestCase, ALUHelpers)
 from soc.fu.spr.pipeline import SPRBasePipe
@@ -90,7 +90,7 @@ class SPRTestCase(FHDLTestCase):
         initial_regs = [0] * 32
         initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678, 'LR': 0x1234,
                         'XER': 0xe00c0000}
-        self.run_tst_program(Program(lst), initial_regs, initial_sprs)
+        self.run_tst_program(Program(lst, bigendian), initial_regs, initial_sprs)
 
     def test_1_mtspr(self):
         lst = ["mtspr 26, 1", # SRR0
@@ -104,7 +104,8 @@ class SPRTestCase(FHDLTestCase):
         initial_regs[4] = 0x1010101010101010
         initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678, 'LR': 0x1234,
                         'XER': 0x0}
-        self.run_tst_program(Program(lst), initial_regs, initial_sprs)
+        self.run_tst_program(Program(lst, bigendian),
+                             initial_regs, initial_sprs)
 
     def test_2_mtspr_mfspr(self):
         lst = ["mtspr 26, 1", # SRR0
@@ -122,7 +123,8 @@ class SPRTestCase(FHDLTestCase):
         initial_regs[4] = 0x1010101010101010
         initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678, 'LR': 0x1234,
                         'XER': 0x0}
-        self.run_tst_program(Program(lst), initial_regs, initial_sprs)
+        self.run_tst_program(Program(lst, bigendian),
+                             initial_regs, initial_sprs)
 
     def test_ilang(self):
         pspec = SPRPipeSpec(id_wid=2)
@@ -163,7 +165,8 @@ class TestRunner(FHDLTestCase):
                 program = test.program
                 self.subTest(test.name)
                 sim = ISA(pdecode2, test.regs, test.sprs, test.cr,
-                                test.mem, test.msr)
+                                test.mem, test.msr,
+                                bigendian=bigendian)
                 gen = program.generate_instructions()
                 instructions = list(zip(gen, program.assembly.splitlines()))
 
@@ -182,7 +185,7 @@ class TestRunner(FHDLTestCase):
                         print ("before: so/ov/32", so, ov, ov32)
 
                     # ask the decoder to decode this binary data (endian'd)
-                    yield pdecode2.dec.bigendian.eq(0)  # little / big?
+                    yield pdecode2.dec.bigendian.eq(bigendian)  # little / big?
                     yield instruction.eq(ins)          # raw binary instr.
                     yield Settle()
 
diff --git a/src/soc/fu/trap/test/test_pipe_caller.py b/src/soc/fu/trap/test/test_pipe_caller.py
index 25514730..552be8f4 100644
--- a/src/soc/fu/trap/test/test_pipe_caller.py
+++ b/src/soc/fu/trap/test/test_pipe_caller.py
@@ -10,7 +10,7 @@ from soc.decoder.power_enums import (XER_bits, Function, InternalOp, CryIn)
 from soc.decoder.selectable_int import SelectableInt
 from soc.simulator.program import Program
 from soc.decoder.isa.all import ISA
-
+from soc.config.endian import bigendian
 
 from soc.fu.test.common import (TestCase, ALUHelpers)
 from soc.fu.trap.pipeline import TrapBasePipe
@@ -86,7 +86,8 @@ class TrapTestCase(FHDLTestCase):
         initial_regs = [0] * 32
         initial_regs[1] = 1
         initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678}
-        self.run_tst_program(Program(lst), initial_regs, initial_sprs)
+        self.run_tst_program(Program(lst, bigendian),
+                             initial_regs, initial_sprs)
 
     def test_0_trap_eq_imm(self):
         insns = ["twi", "tdi"]
@@ -95,7 +96,7 @@ class TrapTestCase(FHDLTestCase):
             lst = [f"{choice} 4, 1, %d" % i] # TO=4: trap equal
             initial_regs = [0] * 32
             initial_regs[1] = 1
-            self.run_tst_program(Program(lst), initial_regs)
+            self.run_tst_program(Program(lst, bigendian), initial_regs)
 
     def test_0_trap_eq(self):
         insns = ["tw", "td"]
@@ -105,26 +106,26 @@ class TrapTestCase(FHDLTestCase):
             initial_regs = [0] * 32
             initial_regs[1] = 1
             initial_regs[2] = 1
-            self.run_tst_program(Program(lst), initial_regs)
+            self.run_tst_program(Program(lst, bigendian), initial_regs)
 
     def test_3_mtmsr_0(self):
         lst = ["mtmsr 1,0"]
         initial_regs = [0] * 32
         initial_regs[1] = 0xffffffffffffffff
-        self.run_tst_program(Program(lst), initial_regs)
+        self.run_tst_program(Program(lst, bigendian), initial_regs)
 
     def test_3_mtmsr_1(self):
         lst = ["mtmsr 1,1"]
         initial_regs = [0] * 32
         initial_regs[1] = 0xffffffffffffffff
-        self.run_tst_program(Program(lst), initial_regs)
+        self.run_tst_program(Program(lst, bigendian), initial_regs)
 
     def test_999_illegal(self):
         # ok, um this is a bit of a cheat: use an instruction we know
         # is not implemented by either ISACaller or the core
         lst = ["tbegin."]
         initial_regs = [0] * 32
-        self.run_tst_program(Program(lst), initial_regs)
+        self.run_tst_program(Program(lst, bigendian), initial_regs)
 
     def test_ilang(self):
         pspec = TrapPipeSpec(id_wid=2)
@@ -164,7 +165,8 @@ class TestRunner(FHDLTestCase):
                 program = test.program
                 self.subTest(test.name)
                 sim = ISA(pdecode2, test.regs, test.sprs, test.cr,
-                                test.mem, test.msr)
+                                test.mem, test.msr,
+                                bigendian=bigendian)
                 gen = program.generate_instructions()
                 instructions = list(zip(gen, program.assembly.splitlines()))
 
@@ -182,7 +184,7 @@ class TestRunner(FHDLTestCase):
                         print ("before: so/ov/32", so, ov, ov32)
 
                     # ask the decoder to decode this binary data (endian'd)
-                    yield pdecode2.dec.bigendian.eq(0)  # little / big?
+                    yield pdecode2.dec.bigendian.eq(bigendian)  # little / big?
                     yield instruction.eq(ins)          # raw binary instr.
                     yield Settle()
                     fn_unit = yield pdecode2.e.do.fn_unit
diff --git a/src/soc/simulator/program.py b/src/soc/simulator/program.py
index ad6ef970..ee5ed7d7 100644
--- a/src/soc/simulator/program.py
+++ b/src/soc/simulator/program.py
@@ -15,7 +15,7 @@ memmap = os.path.join(filedir, "memmap")
 
 
 class Program:
-    def __init__(self, instructions, bigendian=True):
+    def __init__(self, instructions, bigendian):
         self.bigendian = bigendian
         if self.bigendian:
             self.endian_fmt = "elf64-big"
diff --git a/src/soc/simulator/qemu.py b/src/soc/simulator/qemu.py
index 83420aa5..89386ea1 100644
--- a/src/soc/simulator/qemu.py
+++ b/src/soc/simulator/qemu.py
@@ -13,7 +13,7 @@ launch_args_le = ['qemu-system-ppc64le',
 
 
 class QemuController:
-    def __init__(self, kernel, bigendian=True):
+    def __init__(self, kernel, bigendian):
         if bigendian:
             args = launch_args_be + ['-kernel', kernel]
         else:
@@ -22,7 +22,6 @@ class QemuController:
                                            stdout=subprocess.PIPE,
                                            stdin=subprocess.PIPE)
         self.gdb = GdbController(gdb_path='powerpc64-linux-gnu-gdb')
-        self.set_endian(bigendian)
 
     def __enter__(self):
         return self
@@ -112,16 +111,30 @@ class QemuController:
         self.qemu_popen.stdin.close()
 
 
-def run_program(program, initial_mem=None, extra_break_addr=None):
-    q = QemuController(program.binfile.name)
+def run_program(program, initial_mem=None, extra_break_addr=None,
+                         bigendian=False):
+    q = QemuController(program.binfile.name, bigendian)
     q.connect()
+    q.set_endian(True) # how qemu gets/sets data, NOT sets arch
+
     # Run to the start of the program
-    q.break_address(0x20000000)
     if initial_mem:
         for addr, (v, wid) in initial_mem.items():
             for i in range(wid):
                 q.set_byte(addr+i, (v>>i*8) & 0xff)
+
+    # set breakpoint at start
+    q.break_address(0x20000000)
     q.gdb_continue()
+    # set the MSR bit 63, to set bigendian/littleendian mode
+    msr = q.get_msr()
+    print ("msr", bigendian, hex(msr))
+    if bigendian:
+        msr &= ~(1<<0)
+    else:
+        msr |= (1<<0)
+    q.gdb_eval('$msr=%d' % msr)
+    print ("msr set to", hex(msr))
     # set the CR to 0, matching the simulator
     q.gdb_eval('$cr=0')
     # delete the previous breakpoint so loops don't screw things up
@@ -134,11 +147,13 @@ def run_program(program, initial_mem=None, extra_break_addr=None):
     if extra_break_addr:
         q.break_address(extra_break_addr)
     q.gdb_continue()
+    q.set_endian(False) # how qemu gets/sets data, NOT sets arch
+
     return q
 
 
 if __name__ == '__main__':
-    q = QemuController("qemu_test/kernel.bin")
+    q = QemuController("simulator/qemu_test/kernel.bin", bigendian=True)
     q.connect()
     q.break_address(0x20000000)
     q.gdb_continue()
diff --git a/src/soc/simulator/test_helloworld_sim.py b/src/soc/simulator/test_helloworld_sim.py
index 8801844d..fb5ed768 100644
--- a/src/soc/simulator/test_helloworld_sim.py
+++ b/src/soc/simulator/test_helloworld_sim.py
@@ -14,7 +14,7 @@ from soc.simulator.qemu import run_program
 from soc.decoder.isa.all import ISA
 from soc.fu.test.common import TestCase
 from soc.simulator.test_sim import DecoderBase
-
+from soc.config.endian import bigendian
 
 
 class HelloTestCases(FHDLTestCase):
@@ -38,7 +38,8 @@ class HelloTestCases(FHDLTestCase):
                 "mtspr   9, 12",     # mtctr r12
                 "bcctrl  20,0,0", # bctrl
                 ]
-        self.run_tst_program(Program(lst), [1,12], extra_break_addr=0x1014)
+        self.run_tst_program(Program(lst, bigendian),
+                             [1,12], extra_break_addr=0x1014)
 
     def run_tst_program(self, prog, initial_regs=None, initial_sprs=None,
                                     initial_mem=None, extra_break_addr=None):
diff --git a/src/soc/simulator/test_mul_sim.py b/src/soc/simulator/test_mul_sim.py
index a3db0f13..00c51a4e 100644
--- a/src/soc/simulator/test_mul_sim.py
+++ b/src/soc/simulator/test_mul_sim.py
@@ -14,6 +14,7 @@ from soc.simulator.qemu import run_program
 from soc.decoder.isa.all import ISA
 from soc.fu.test.common import TestCase
 from soc.simulator.test_sim import DecoderBase
+from soc.config.endian import bigendian
 
 
 
@@ -28,7 +29,7 @@ class MulTestCases(FHDLTestCase):
         lst = ["addi 1, 0, 0x5678",
                "addi 2, 0, 0x1234",
                "mullw 3, 1, 2"]
-        self.run_tst_program(Program(lst), [3])
+        self.run_tst_program(Program(lst, bigendian), [3])
 
     def test_mullwo(self):
         lst = ["addi 1, 0, 0x5678",
@@ -36,7 +37,7 @@ class MulTestCases(FHDLTestCase):
                "addi 2, 0, 0x1234",
                "neg 2, 2",
                "mullwo 3, 1, 2"]
-        self.run_tst_program(Program(lst), [3])
+        self.run_tst_program(Program(lst, bigendian), [3])
 
     def run_tst_program(self, prog, initial_regs=None, initial_sprs=None,
                                     initial_mem=None):
diff --git a/src/soc/simulator/test_sim.py b/src/soc/simulator/test_sim.py
index 7fa0c8a8..d1e65f4f 100644
--- a/src/soc/simulator/test_sim.py
+++ b/src/soc/simulator/test_sim.py
@@ -13,6 +13,7 @@ from soc.simulator.program import Program
 from soc.simulator.qemu import run_program
 from soc.decoder.isa.all import ISA
 from soc.fu.test.common import TestCase
+from soc.config.endian import bigendian
 
 
 class AttnTestCase(FHDLTestCase):
@@ -30,7 +31,7 @@ class AttnTestCase(FHDLTestCase):
                "subf. 1, 6, 7",
                "cmp cr2, 1, 6, 7",
                ]
-        with Program(lst) as program:
+        with Program(lst, bigendian) as program:
             self.run_tst_program(program, [1])
 
     def run_tst_program(self, prog, initial_regs=None, initial_sprs=None,
@@ -55,7 +56,7 @@ class GeneralTestCases(FHDLTestCase):
                "subf. 1, 6, 7",
                "cmp cr2, 1, 6, 7",
                ]
-        with Program(lst) as program:
+        with Program(lst, bigendian) as program:
             self.run_tst_program(program, [1])
 
     @unittest.skip("disable")
@@ -64,7 +65,7 @@ class GeneralTestCases(FHDLTestCase):
                "addi 2, 0, 0x1234",
                "add  3, 1, 2",
                "and  4, 1, 2"]
-        with Program(lst) as program:
+        with Program(lst, bigendian) as program:
             self.run_tst_program(program, [1, 2, 3, 4])
 
     @unittest.skip("disable")
@@ -77,7 +78,7 @@ class GeneralTestCases(FHDLTestCase):
         initial_mem = {0x1230: (0x5432123412345678, 8),
                        0x1238: (0xabcdef0187654321, 8),
                       }
-        with Program(lst) as program:
+        with Program(lst, bigendian) as program:
             self.run_tst_program(program,
                                  [1, 2, 3],
                                  initial_mem)
@@ -89,7 +90,7 @@ class GeneralTestCases(FHDLTestCase):
                "addi 4, 0, 0x40",
                "stw  1, 0x40(2)",
                "lwbrx  3, 4, 2"]
-        with Program(lst) as program:
+        with Program(lst, bigendian) as program:
             self.run_tst_program(program, [1, 2, 3])
 
     @unittest.skip("disable")
@@ -99,7 +100,7 @@ class GeneralTestCases(FHDLTestCase):
                "addi 4, 0, 0x40",
                "stwbrx  1, 4, 2",
                "lwzx  3, 4, 2"]
-        with Program(lst) as program:
+        with Program(lst, bigendian) as program:
             self.run_tst_program(program, [1, 2, 3])
 
     @unittest.skip("disable")
@@ -109,7 +110,7 @@ class GeneralTestCases(FHDLTestCase):
                "addi 4, 0, 0x40",
                "stw  1, 0x40(2)",
                "lwzx  3, 4, 2"]
-        with Program(lst) as program:
+        with Program(lst, bigendian) as program:
             self.run_tst_program(program, [1, 2, 3])
 
     @unittest.skip("disable")
@@ -124,7 +125,7 @@ class GeneralTestCases(FHDLTestCase):
                "addi 5, 0, 0x12",
                "stb 5, 5(2)",
                "ld  5, 0(2)"]
-        with Program(lst) as program:
+        with Program(lst, bigendian) as program:
             self.run_tst_program(program, [1, 2, 3, 4, 5])
 
     @unittest.skip("disable")
@@ -134,7 +135,7 @@ class GeneralTestCases(FHDLTestCase):
                "subf 3, 1, 2",
                "subfic 4, 1, 0x1337",
                "neg 5, 1"]
-        with Program(lst) as program:
+        with Program(lst, bigendian) as program:
             self.run_tst_program(program, [1, 2, 3, 4, 5])
 
     @unittest.skip("disable")
@@ -146,7 +147,7 @@ class GeneralTestCases(FHDLTestCase):
                "addc 3, 2, 1",
                "addi 3, 3, 1"
                ]
-        with Program(lst) as program:
+        with Program(lst, bigendian) as program:
             self.run_tst_program(program, [1, 2, 3])
 
     @unittest.skip("disable")
@@ -154,7 +155,7 @@ class GeneralTestCases(FHDLTestCase):
         lst = ["addi 1, 0, 0x0FFF",
                "addis 1, 1, 0x0F"
                ]
-        with Program(lst) as program:
+        with Program(lst, bigendian) as program:
             self.run_tst_program(program, [1])
 
     @unittest.skip("broken")
@@ -162,7 +163,7 @@ class GeneralTestCases(FHDLTestCase):
         lst = ["addi 1, 0, 3",
                "mulli 1, 1, 2"
                ]
-        with Program(lst) as program:
+        with Program(lst, bigendian) as program:
             self.run_tst_program(program, [1])
 
     @unittest.skip("disable")
@@ -181,7 +182,7 @@ class GeneralTestCases(FHDLTestCase):
                        0x1008: (0xabcdef0187654321, 8),
                        0x1020: (0x1828384822324252, 8),
                         }
-        with Program(lst) as program:
+        with Program(lst, bigendian) as program:
             self.run_tst_program(program, [3,4], initial_mem)
 
     @unittest.skip("disable")
@@ -199,7 +200,7 @@ class GeneralTestCases(FHDLTestCase):
                        0x1008: (0xabcdef0187654321, 8),
                        0x1020: (0x1828384822324252, 8),
                         }
-        with Program(lst) as program:
+        with Program(lst, bigendian) as program:
             self.run_tst_program(program, [1,2,3,4], initial_mem)
 
     def test_loop(self):
@@ -217,14 +218,14 @@ class GeneralTestCases(FHDLTestCase):
                "cmpi 0,1,9,12",     # compare 9 to value 0, store in CR2
                "bc 4,0,-8"         # branch if CR2 "test was != 0"
                ]
-        with Program(lst) as program:
+        with Program(lst, bigendian) as program:
             self.run_tst_program(program, [9], initial_mem={})
 
     def test_30_addis(self):
         lst = [#"addi 0, 0, 5",
                "addis 12, 0, 0",
                ]
-        with Program(lst) as program:
+        with Program(lst, bigendian) as program:
             self.run_tst_program(program, [12])
 
     def run_tst_program(self, prog, initial_regs=None, initial_sprs=None,
@@ -244,7 +245,6 @@ class DecoderBase:
         gen = list(generator.generate_instructions())
         insn_code = generator.assembly.splitlines()
         instructions = list(zip(gen, insn_code))
-        bigendian = False
 
         pdecode = create_pdecode()
         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
@@ -261,7 +261,7 @@ class DecoderBase:
         sim = Simulator(m)
 
         def process():
-            #yield pdecode2.dec.bigendian.eq(1)
+            #yield pdecode2.dec.bigendian.eq(bigendian)
             yield Settle()
 
             while True:
@@ -287,7 +287,8 @@ class DecoderBase:
         simulator = self.run_tst(prog, initial_mem=initial_mem,
                                  initial_pc=0x20000000)
         prog.reset()
-        with run_program(prog, initial_mem, extra_break_addr) as q:
+        with run_program(prog, initial_mem, extra_break_addr,
+                         bigendian=bigendian) as q:
             self.qemu_register_compare(simulator, q, reglist)
             self.qemu_mem_compare(simulator, q, True)
         print(simulator.gpr.dump())