From: Sahand Kashani <sahand.kashani@gmail.com>
Date: Wed, 8 Apr 2020 21:50:37 +0000 (+0200)
Subject: Merge branch 'master' of github.com:YosysHQ/yosys into firrtl_backend_fileinfo
X-Git-Tag: working-ls180~630^2~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9edf8869c18951ec2b75f074065f073da3253244;p=yosys.git

Merge branch 'master' of github.com:YosysHQ/yosys into firrtl_backend_fileinfo
---

9edf8869c18951ec2b75f074065f073da3253244
diff --cc backends/firrtl/firrtl.cc
index 3ef886664,1f750b359..94d3e14c1
--- a/backends/firrtl/firrtl.cc
+++ b/backends/firrtl/firrtl.cc
@@@ -411,12 -400,10 +411,12 @@@ struct FirrtlWorke
  		for (auto wire : module->wires())
  		{
  			const auto wireName = make_id(wire->name);
 +			std::string wireFileinfo = getFileinfo(wire);
 +
  			// If a wire has initial data, issue a warning since FIRRTL doesn't currently support it.
- 			if (wire->attributes.count("\\init")) {
+ 			if (wire->attributes.count(ID::init)) {
  				log_warning("Initial value (%s) for (%s.%s) not supported\n",
- 							wire->attributes.at("\\init").as_string().c_str(),
+ 							wire->attributes.at(ID::init).as_string().c_str(),
  							log_id(module), log_id(wire));
  			}
  			if (wire->port_id)
@@@ -454,12 -441,11 +454,12 @@@
  			string primop;
  			bool always_uint = false;
  			string y_id = make_id(cell->name);
 +			std::string cellFileinfo = getFileinfo(cell);
  
- 			if (cell->type.in("$not", "$logic_not", "$neg", "$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_bool", "$reduce_xnor"))
+ 			if (cell->type.in(ID($not), ID($logic_not), ID($neg), ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_bool), ID($reduce_xnor)))
  			{
- 				string a_expr = make_expr(cell->getPort("\\A"));
+ 				string a_expr = make_expr(cell->getPort(ID::A));
 -				wire_decls.push_back(stringf("    wire %s: UInt<%d>\n", y_id.c_str(), y_width));
 +				wire_decls.push_back(stringf("    wire %s: UInt<%d> %s\n", y_id.c_str(), y_width, cellFileinfo.c_str()));
  
  				if (a_signed) {
  					a_expr = "asSInt(" + a_expr + ")";
@@@ -477,18 -463,18 +477,18 @@@
  					primop = "neg";
  					firrtl_is_signed = true;	// Result of "neg" is signed (an SInt).
  					firrtl_width = a_width;
- 				} else if (cell->type == "$logic_not") {
+ 				} else if (cell->type == ID($logic_not)) {
 -                                        primop = "eq";
 -                                        a_expr = stringf("%s, UInt(0)", a_expr.c_str());
 -                                }
 +					primop = "eq";
 +					a_expr = stringf("%s, UInt(0)", a_expr.c_str());
 +				}
- 				else if (cell->type == "$reduce_and") primop = "andr";
- 				else if (cell->type == "$reduce_or") primop = "orr";
- 				else if (cell->type == "$reduce_xor") primop = "xorr";
- 				else if (cell->type == "$reduce_xnor") {
+ 				else if (cell->type == ID($reduce_and)) primop = "andr";
+ 				else if (cell->type == ID($reduce_or)) primop = "orr";
+ 				else if (cell->type == ID($reduce_xor)) primop = "xorr";
+ 				else if (cell->type == ID($reduce_xnor)) {
 -                                        primop = "not";
 -                                        a_expr = stringf("xorr(%s)", a_expr.c_str());
 -                                }
 +					primop = "not";
 +					a_expr = stringf("xorr(%s)", a_expr.c_str());
 +				}
- 				else if (cell->type == "$reduce_bool") {
+ 				else if (cell->type == ID($reduce_bool)) {
  					primop = "neq";
  					// Use the sign of the a_expr and its width as the type (UInt/SInt) and width of the comparand.
  					a_expr = stringf("%s, %cInt<%d>(0)", a_expr.c_str(), a_signed ? 'S' : 'U', a_width);
@@@ -499,19 -485,18 +499,19 @@@
  				if ((firrtl_is_signed && !always_uint))
  					expr = stringf("asUInt(%s)", expr.c_str());
  
 -				cell_exprs.push_back(stringf("    %s <= %s\n", y_id.c_str(), expr.c_str()));
 +				cell_exprs.push_back(stringf("    %s <= %s %s\n", y_id.c_str(), expr.c_str(), cellFileinfo.c_str()));
- 				register_reverse_wire_map(y_id, cell->getPort("\\Y"));
+ 				register_reverse_wire_map(y_id, cell->getPort(ID::Y));
  
  				continue;
  			}
- 			if (cell->type.in("$add", "$sub", "$mul", "$div", "$mod", "$xor", "$xnor", "$and", "$or", "$eq", "$eqx",
- 				"$gt", "$ge", "$lt", "$le", "$ne", "$nex", "$shr", "$sshr", "$sshl", "$shl",
- 				"$logic_and", "$logic_or", "$pow"))
+ 			if (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($xor), ID($xnor), ID($and), ID($or), ID($eq), ID($eqx),
 -							  ID($gt), ID($ge), ID($lt), ID($le), ID($ne), ID($nex), ID($shr), ID($sshr), ID($sshl), ID($shl),
 -							  ID($logic_and), ID($logic_or), ID($pow)))
++												ID($gt), ID($ge), ID($lt), ID($le), ID($ne), ID($nex), ID($shr), ID($sshr), ID($sshl), ID($shl),
++												ID($logic_and), ID($logic_or), ID($pow)))
  			{
- 				string a_expr = make_expr(cell->getPort("\\A"));
- 				string b_expr = make_expr(cell->getPort("\\B"));
+ 				string a_expr = make_expr(cell->getPort(ID::A));
+ 				string b_expr = make_expr(cell->getPort(ID::B));
 -				wire_decls.push_back(stringf("    wire %s: UInt<%d>\n", y_id.c_str(), y_width));
 +				std::string cellFileinfo = getFileinfo(cell);
 +				wire_decls.push_back(stringf("    wire %s: UInt<%d> %s\n", y_id.c_str(), y_width, cellFileinfo.c_str()));
  
  				if (a_signed) {
  					a_expr = "asSInt(" + a_expr + ")";
@@@ -727,24 -712,24 +727,24 @@@
  				if ((firrtl_is_signed && !always_uint))
  					expr = stringf("asUInt(%s)", expr.c_str());
  
 -				cell_exprs.push_back(stringf("    %s <= %s\n", y_id.c_str(), expr.c_str()));
 +				cell_exprs.push_back(stringf("    %s <= %s %s\n", y_id.c_str(), expr.c_str(), cellFileinfo.c_str()));
- 				register_reverse_wire_map(y_id, cell->getPort("\\Y"));
+ 				register_reverse_wire_map(y_id, cell->getPort(ID::Y));
  
  				continue;
  			}
  
- 			if (cell->type.in("$mux"))
+ 			if (cell->type.in(ID($mux)))
  			{
- 				int width = cell->parameters.at("\\WIDTH").as_int();
- 				string a_expr = make_expr(cell->getPort("\\A"));
- 				string b_expr = make_expr(cell->getPort("\\B"));
- 				string s_expr = make_expr(cell->getPort("\\S"));
+ 				int width = cell->parameters.at(ID::WIDTH).as_int();
+ 				string a_expr = make_expr(cell->getPort(ID::A));
+ 				string b_expr = make_expr(cell->getPort(ID::B));
+ 				string s_expr = make_expr(cell->getPort(ID::S));
 -				wire_decls.push_back(stringf("    wire %s: UInt<%d>\n", y_id.c_str(), width));
 +				wire_decls.push_back(stringf("    wire %s: UInt<%d> %s\n", y_id.c_str(), width, cellFileinfo.c_str()));
  
  				string expr = stringf("mux(%s, %s, %s)", s_expr.c_str(), b_expr.c_str(), a_expr.c_str());
  
 -				cell_exprs.push_back(stringf("    %s <= %s\n", y_id.c_str(), expr.c_str()));
 +				cell_exprs.push_back(stringf("    %s <= %s %s\n", y_id.c_str(), expr.c_str(), cellFileinfo.c_str()));
- 				register_reverse_wire_map(y_id, cell->getPort("\\Y"));
+ 				register_reverse_wire_map(y_id, cell->getPort(ID::Y));
  
  				continue;
  			}
@@@ -878,14 -863,14 +878,14 @@@
  				if (clkpol == false)
  					log_error("Negative edge clock on FF %s.%s.\n", log_id(module), log_id(cell));
  
- 				int width = cell->parameters.at("\\WIDTH").as_int();
- 				string expr = make_expr(cell->getPort("\\D"));
- 				string clk_expr = "asClock(" + make_expr(cell->getPort("\\CLK")) + ")";
+ 				int width = cell->parameters.at(ID::WIDTH).as_int();
+ 				string expr = make_expr(cell->getPort(ID::D));
+ 				string clk_expr = "asClock(" + make_expr(cell->getPort(ID::CLK)) + ")";
  
 -				wire_decls.push_back(stringf("    reg %s: UInt<%d>, %s\n", y_id.c_str(), width, clk_expr.c_str()));
 +				wire_decls.push_back(stringf("    reg %s: UInt<%d>, %s %s\n", y_id.c_str(), width, clk_expr.c_str(), cellFileinfo.c_str()));
  
 -				cell_exprs.push_back(stringf("    %s <= %s\n", y_id.c_str(), expr.c_str()));
 +				cell_exprs.push_back(stringf("    %s <= %s %s\n", y_id.c_str(), expr.c_str(), cellFileinfo.c_str()));
- 				register_reverse_wire_map(y_id, cell->getPort("\\Q"));
+ 				register_reverse_wire_map(y_id, cell->getPort(ID::Q));
  
  				continue;
  			}