From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 26 Apr 2021 08:22:14 +0000 (+0100)
Subject: simplify dcache test
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9eea4c782d498e8944c4407a7a48154236d46868;p=soc.git

simplify dcache test
---

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index 4d59a07a..aea4a28b 100644
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -1794,18 +1794,15 @@ def dcache_regression_sim(dut, mem):
     yield
     yield
 
-    addr = 6
-    data = ~i
-    sim_mem[addr] = data
+    addr = 1
     row = addr
     addr *= 8
 
-    print ("random testing %d 0x%x row %d data 0x%x" % (i, addr, row, data))
+    print ("random testing %d 0x%x row %d" % (i, addr, row))
 
     yield from dcache_load(dut, addr)
-    #yield from dcache_store(dut, addr, data)
 
-    addr = 7
+    addr = 2
     sim_data = sim_mem[addr]
     row = addr
     addr *= 8
@@ -1817,7 +1814,6 @@ def dcache_regression_sim(dut, mem):
 
 
 
-
 def dcache_sim(dut, mem):
     # clear stuff
     yield dut.d_in.valid.eq(0)