From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 9 Oct 2018 15:17:42 +0000 (+0100)
Subject: add explanatory comment
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9eeff1d828aab42dd6ec94aafacf68bc206e81c8;p=riscv-isa-sim.git

add explanatory comment
---

diff --git a/riscv/insn_template_sv.cc b/riscv/insn_template_sv.cc
index 27634e1..f96f117 100644
--- a/riscv/insn_template_sv.cc
+++ b/riscv/insn_template_sv.cc
@@ -50,7 +50,8 @@
    the state machine *also* copes with cases where registers are marked
    *specifically* as "redirected but still scalar", and the twin-predication
    version can also skip forward so that a scalar can be matched up with
-   a single bit-predicated vector.
+   a single bit-predicated vector (scalar source, single-bit-predicated
+   dest *or* the other way round).
 
    it's *really* comprehensive in other words, for just 200 or so lines.
  */