From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 27 Jun 2020 19:12:02 +0000 (+0100)
Subject: increase (double) address width in TstL0CacheBuffer
X-Git-Tag: div_pipeline~236
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9ef2e379843af6add4d3a34a7b2ef567d26b21fc;p=soc.git

increase (double) address width in TstL0CacheBuffer
---

diff --git a/src/soc/experiment/l0_cache.py b/src/soc/experiment/l0_cache.py
index c356e29b..f42545d5 100644
--- a/src/soc/experiment/l0_cache.py
+++ b/src/soc/experiment/l0_cache.py
@@ -266,7 +266,7 @@ class L0CacheBuffer(Elaboratable):
 class TstL0CacheBuffer(Elaboratable):
     def __init__(self, n_units=3, regwid=16, addrwid=4, ifacetype='testpi'):
         pspec = TestMemPspec(ldst_ifacetype=ifacetype,
-                             addr_wid=addrwid,
+                             addr_wid=addrwid<<1,
                              mask_wid=8,
                              reg_wid=regwid)
         self.cmpi = ConfigMemoryPortInterface(pspec)