From: Gabe Black <gblack@eecs.umich.edu>
Date: Fri, 10 Nov 2006 10:49:16 +0000 (-0500)
Subject: Actually finished moving the register file stuff around.
X-Git-Tag: m5_2.0_beta2~66^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9ef51f2dbaba88c10366d708f0ca872bb39064e4;p=gem5.git

Actually finished moving the register file stuff around.

--HG--
extra : convert_revision : 786735ecea8ff480db6b3754ac5daa562938d988
---

diff --git a/src/arch/alpha/floatregfile.hh b/src/arch/alpha/floatregfile.hh
index 6b394da03..d289f5785 100644
--- a/src/arch/alpha/floatregfile.hh
+++ b/src/arch/alpha/floatregfile.hh
@@ -42,6 +42,11 @@ class Checkpoint;
 
 namespace AlphaISA
 {
+    static inline std::string getFloatRegName(RegIndex)
+    {
+        return "";
+    }
+
     class FloatRegFile
     {
       public:
diff --git a/src/arch/alpha/intregfile.hh b/src/arch/alpha/intregfile.hh
index 78f666345..0d65f69e0 100644
--- a/src/arch/alpha/intregfile.hh
+++ b/src/arch/alpha/intregfile.hh
@@ -41,6 +41,11 @@ class Checkpoint;
 
 namespace AlphaISA
 {
+    static inline std::string getIntRegName(RegIndex)
+    {
+        return "";
+    }
+
     // redirected register map, really only used for the full system case.
     extern const int reg_redir[NumIntRegs];
 
diff --git a/src/arch/alpha/miscregfile.hh b/src/arch/alpha/miscregfile.hh
index 85cb054bb..31b3e59b3 100644
--- a/src/arch/alpha/miscregfile.hh
+++ b/src/arch/alpha/miscregfile.hh
@@ -54,6 +54,11 @@ namespace AlphaISA
         MISCREG_INTR
     };
 
+    static inline std::string getMiscRegName(RegIndex)
+    {
+        return "";
+    }
+
     class MiscRegFile {
       protected:
         uint64_t	fpcr;		// floating point condition codes
diff --git a/src/arch/alpha/regfile.hh b/src/arch/alpha/regfile.hh
index 091f0e2e6..ff5830822 100644
--- a/src/arch/alpha/regfile.hh
+++ b/src/arch/alpha/regfile.hh
@@ -32,6 +32,7 @@
 #define __ARCH_ALPHA_REGFILE_HH__
 
 #include "arch/alpha/isa_traits.hh"
+#include "arch/alpha/floatregfile.hh"
 #include "arch/alpha/intregfile.hh"
 #include "arch/alpha/miscregfile.hh"
 #include "arch/alpha/types.hh"
@@ -47,38 +48,6 @@ class ThreadContext;
 namespace AlphaISA
 {
 
-    static inline std::string getIntRegName(RegIndex)
-    {
-        return "";
-    }
-
-    static inline std::string getFloatRegName(RegIndex)
-    {
-        return "";
-    }
-
-    static inline std::string getMiscRegName(RegIndex)
-    {
-        return "";
-    }
-
-    class FloatRegFile
-    {
-      public:
-
-        union {
-            uint64_t q[NumFloatRegs];	// integer qword view
-            double d[NumFloatRegs];	// double-precision floating point view
-        };
-
-        void serialize(std::ostream &os);
-
-        void unserialize(Checkpoint *cp, const std::string &section);
-
-        void clear()
-        { bzero(d, sizeof(d)); }
-    };
-
     class RegFile {
 
       protected: