From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 1 Feb 2021 21:23:22 +0000 (+0000)
Subject: ISACaller, in svp64 mode, read the next 32 bits when SVP64 identified
X-Git-Tag: convert-csv-opcode-to-binary~266
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9f19947c9887e61f66247ee1ce82ae60bedaf3c6;p=soc.git

ISACaller, in svp64 mode, read the next 32 bits when SVP64 identified
---

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index c58ad248..7730ce19 100644
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -325,6 +325,7 @@ class ISACaller:
 
         self.bigendian = bigendian
         self.halted = False
+        self.is_svp64_mode = False
         self.respect_pc = respect_pc
         if initial_sprs is None:
             initial_sprs = {}
@@ -607,22 +608,37 @@ class ISACaller:
         yield self.dec2.state.msr.eq(self.msr.value)
         yield self.dec2.state.pc.eq(pc)
 
-        # SVP64.  first, check if the opcode is EXT001
+        # SVP64.  first, check if the opcode is EXT001, and SVP64 id bits set
         yield Settle()
         opcode = yield self.dec2.dec.opcode_in
         pfx = SVP64PrefixFields()
         pfx.insn.value = opcode
         major = pfx.major.asint(msb0=True) # MSB0 inversion
         print ("prefix test: opcode:", major, bin(major),
-                pfx.insn[7] == 0b1, pfx.insn[9] == 0b1,
-                bin(pfx.rm.asint(msb0=True)))
+                pfx.insn[7] == 0b1, pfx.insn[9] == 0b1)
+        self.is_svp64_mode = ((major == 0b000001) and
+                              pfx.insn[7].value == 0b1 and
+                              pfx.insn[9].value == 0b1)
+        if not self.is_svp64_mode:
+            return
+
+        # in SVP64 mode.  decode/print out svp64 prefix, get v3.0B instruction
+        print ("svp64.rm", bin(pfx.rm.asint(msb0=True)))
+        ins = self.imem.ld(pc+4, 4, False, True)
+        print("     svsetup: 0x%x 0x%x %s" % (pc+4, ins & 0xffffffff, bin(ins)))
+        yield self.dec2.dec.raw_opcode_in.eq(ins & 0xffffffff)
+        yield Settle()
 
     def execute_one(self):
         """execute one instruction
         """
         # get the disassembly code for this instruction
-        code = self.disassembly[self._pc]
-        print("sim-execute", hex(self._pc), code)
+        if self.is_svp64_mode:
+            code = self.disassembly[self._pc+4]
+            print("    svp64 sim-execute", hex(self._pc), code)
+        else:
+            code = self.disassembly[self._pc]
+            print("sim-execute", hex(self._pc), code)
         opname = code.split(' ')[0]
         yield from self.call(opname)
 
diff --git a/src/soc/decoder/selectable_int.py b/src/soc/decoder/selectable_int.py
index 7f60f5e4..152764ca 100644
--- a/src/soc/decoder/selectable_int.py
+++ b/src/soc/decoder/selectable_int.py
@@ -302,7 +302,7 @@ class SelectableInt:
             #print ("__getitem__ slice num bits", start, stop, bits)
             mask = (1 << bits) - 1
             value = (self.value >> start) & mask
-            print("getitem", key, self.bits, hex(self.value), value)
+            print("getitem", stop, start, self.bits, hex(self.value), value)
             return SelectableInt(value, bits)
 
     def __setitem__(self, key, value):