From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 9 Aug 2019 17:32:12 +0000 (-0700)
Subject: opt_expr -fine to trim LSBs of $alu too
X-Git-Tag: working-ls180~1149^2~6
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9f1b82f5941778a3691ce0ef08e0d06547451110;p=yosys.git

opt_expr -fine to trim LSBs of $alu too
---

diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index acdc39937..5a82b7066 100644
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -642,26 +642,31 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 				}
 			}
 
-			if (cell->type.in("$add", "$sub")) {
+			if (cell->type.in("$add", "$sub", "$alu"))
+			{
 				RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
 				RTLIL::SigSpec sig_b = assign_map(cell->getPort("\\B"));
 				RTLIL::SigSpec sig_y = cell->getPort("\\Y");
-				bool sub = cell->type == "$sub";
+				bool ignore_a = cell->type == "$sub" || (cell->type == "$alu" && !cell->getPort("\\BI").is_fully_zero());
 
 				int i;
 				for (i = 0; i < GetSize(sig_y); i++) {
 					if (sig_b.at(i, State::Sx) == State::S0 && sig_a.at(i, State::Sx) != State::Sx)
 						module->connect(sig_y[i], sig_a[i]);
-					else if (!sub && sig_a.at(i, State::Sx) == State::S0 && sig_b.at(i, State::Sx) != State::Sx)
+					else if (!ignore_a && sig_a.at(i, State::Sx) == State::S0 && sig_b.at(i, State::Sx) != State::Sx)
 						module->connect(sig_y[i], sig_b[i]);
 					else
 						break;
 				}
 				if (i > 0) {
-					cover_list("opt.opt_expr.fine", "$add", "$sub", cell->type.str());
+					cover_list("opt.opt_expr.fine", "$add", "$sub", "$alu", cell->type.str());
 					cell->setPort("\\A", sig_a.extract_end(i));
 					cell->setPort("\\B", sig_b.extract_end(i));
 					cell->setPort("\\Y", sig_y.extract_end(i));
+					if (cell->type == "$alu") {
+						cell->setPort("\\X", cell->getPort("\\X").extract_end(i));
+						cell->setPort("\\CO", cell->getPort("\\CO").extract_end(i));
+					}
 					cell->fixup_parameters();
 					did_something = true;
 				}