From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 12 Jun 2019 23:33:05 +0000 (-0700)
Subject: Revert "Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux"
X-Git-Tag: working-ls180~1237^2~137
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9f275c1437cb48c28b717f0996edab9da9e73aa0;p=yosys.git

Revert "Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux"

This reverts commit 2223ca91b0cc559bb876e8e97372a8f77da1603e, reversing
changes made to eaee250a6e63e58dfef63fa30c4120db78223e24.
---

diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v
deleted file mode 100644
index 7c189fff8..000000000
--- a/tests/various/muxpack.v
+++ /dev/null
@@ -1,112 +0,0 @@
-module mux_if_unbal_4_1 #(parameter N=4, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
-always @*
-    if (s == 0) o <= i[0*W+:W];
-    else if (s == 1) o <= i[1*W+:W];
-    else if (s == 2) o <= i[2*W+:W];
-    else if (s == 3) o <= i[3*W+:W];
-    else o <= {W{1'bx}};
-endmodule
-
-module mux_if_unbal_5_3 #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
-always @* begin
-    o <= {W{1'bx}};
-    if (s == 0) o <= i[0*W+:W];
-    if (s == 1) o <= i[1*W+:W];
-    if (s == 2) o <= i[2*W+:W];
-    if (s == 3) o <= i[3*W+:W];
-    if (s == 4) o <= i[4*W+:W];
-end
-endmodule
-
-module mux_if_unbal_5_3_invert #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
-always @*
-    if (s != 0) 
-	   	if (s != 1) 
-			if (s != 2)
-				if (s != 3)
-					if (s != 4) o <= i[4*W+:W];
-					else o <= i[0*W+:W];
-				else o <= i[3*W+:W];
-			else o <= i[2*W+:W];
-		else o <= i[1*W+:W];
-    else o <= {W{1'bx}};
-endmodule
-
-module mux_if_unbal_5_3_width_mismatch #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
-always @* begin
-    o <= {W{1'bx}};
-    if (s == 0) o <= i[0*W+:W];
-    if (s == 1) o <= i[1*W+:W];
-    if (s == 2) o[W-2:0] <= i[2*W+:W-1];
-    if (s == 3) o <= i[3*W+:W];
-    if (s == 4) o <= i[4*W+:W];
-end
-endmodule
-
-module mux_if_unbal_4_1_missing #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
-always @* begin
-    if (s == 0) o <= i[0*W+:W];
-//    else if (s == 1) o <= i[1*W+:W];
-//    else if (s == 2) o <= i[2*W+:W];
-    else if (s == 3) o <= i[3*W+:W];
-    else o <= {W{1'bx}};
-end
-endmodule
-
-module mux_if_unbal_5_3_order #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
-always @* begin
-    o <= {W{1'bx}};
-    if (s == 3) o <= i[3*W+:W];
-    if (s == 2) o <= i[2*W+:W];
-    if (s == 1) o <= i[1*W+:W];
-    if (s == 4) o <= i[4*W+:W];
-    if (s == 0) o <= i[0*W+:W];
-end
-endmodule
-
-module mux_if_unbal_4_1_nonexcl #(parameter N=4, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
-always @*
-    if (s == 0) o <= i[0*W+:W];
-    else if (s == 1) o <= i[1*W+:W];
-    else if (s == 2) o <= i[2*W+:W];
-    else if (s == 3) o <= i[3*W+:W];
-	else if (s == 0) o <= {W{1'b0}};
-    else o <= {W{1'bx}};
-endmodule
-
-module mux_if_unbal_5_3_nonexcl #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
-always @* begin
-    o <= {W{1'bx}};
-    if (s == 0) o <= i[0*W+:W];
-    if (s == 1) o <= i[1*W+:W];
-    if (s == 2) o <= i[2*W+:W];
-    if (s == 3) o <= i[3*W+:W];
-    if (s == 4) o <= i[4*W+:W];
-	if (s == 0) o <= i[2*W+:W];
-end
-endmodule
-
-module mux_case_unbal_8_7#(parameter N=8, parameter W=7) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
-always @* begin
-    o <= {W{1'bx}};
-    case (s)
-    0: o <= i[0*W+:W];
-    default:
-        case (s)
-        1: o <= i[1*W+:W];
-        2: o <= i[2*W+:W];
-        default:
-            case (s)
-            3: o <= i[3*W+:W];
-            4: o <= i[4*W+:W];
-            5: o <= i[5*W+:W];
-            default:
-                case (s)
-                    6: o <= i[6*W+:W];
-                    default: o <= i[7*W+:W];
-                endcase
-            endcase
-        endcase
-    endcase
-end
-endmodule
diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys
deleted file mode 100644
index 0c5b82818..000000000
--- a/tests/various/muxpack.ys
+++ /dev/null
@@ -1,135 +0,0 @@
-read_verilog muxpack.v
-design -save read
-hierarchy -top mux_if_unbal_4_1
-prep
-design -save gold
-muxpack
-opt
-stat
-select -assert-count 0 t:$mux
-select -assert-count 1 t:$pmux
-design -stash gate
-design -import gold -as gold
-design -import gate -as gate
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -show-ports miter
-
-design -load read
-hierarchy -top mux_if_unbal_5_3
-prep
-design -save gold
-muxpack
-opt
-stat
-select -assert-count 0 t:$mux
-select -assert-count 1 t:$pmux
-design -stash gate
-design -import gold -as gold
-design -import gate -as gate
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -show-ports miter
-
-design -load read
-hierarchy -top mux_if_unbal_5_3_invert
-prep
-design -save gold
-muxpack
-opt
-stat
-select -assert-count 0 t:$mux
-select -assert-count 1 t:$pmux
-design -stash gate
-design -import gold -as gold
-design -import gate -as gate
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -show-ports miter
-
-design -load read
-hierarchy -top mux_if_unbal_5_3_width_mismatch
-prep
-design -save gold
-muxpack
-opt
-stat
-select -assert-count 0 t:$mux
-select -assert-count 2 t:$pmux
-design -stash gate
-design -import gold -as gold
-design -import gate -as gate
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -show-ports miter
-
-design -load read
-hierarchy -top mux_if_unbal_4_1_missing
-prep
-design -save gold
-muxpack
-opt
-stat
-select -assert-count 0 t:$mux
-select -assert-count 1 t:$pmux
-design -stash gate
-design -import gold -as gold
-design -import gate -as gate
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -show-ports miter
-
-design -load read
-hierarchy -top mux_if_unbal_5_3_order
-prep
-design -save gold
-muxpack
-opt
-stat
-select -assert-count 0 t:$mux
-select -assert-count 1 t:$pmux
-design -stash gate
-design -import gold -as gold
-design -import gate -as gate
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -show-ports miter
-
-design -load read
-hierarchy -top mux_if_unbal_4_1_nonexcl
-prep
-design -save gold
-muxpack
-opt
-stat
-select -assert-count 0 t:$mux
-select -assert-count 1 t:$pmux
-design -stash gate
-design -import gold -as gold
-design -import gate -as gate
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -show-ports miter
-
-design -load read
-hierarchy -top mux_if_unbal_5_3_nonexcl
-prep
-design -save gold
-muxpack
-opt
-stat
-select -assert-count 0 t:$mux
-select -assert-count 1 t:$pmux
-design -stash gate
-design -import gold -as gold
-design -import gate -as gate
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -show-ports miter
-
-design -load read
-hierarchy -top mux_case_unbal_8_7
-prep
-design -save gold
-muxpack
-opt
-stat
-select -assert-count 0 t:$mux
-select -assert-count 1 t:$pmux
-design -stash gate
-design -import gold -as gold
-design -import gate -as gate
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -show-ports miter