From: Thomas Preud'homme Date: Thu, 9 Nov 2017 16:34:43 +0000 (+0000) Subject: [ARM] Fix cmse_nonsecure_entry return insn size X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9f28fe39be68ca484d025ff49f783f050a0a2360;p=gcc.git [ARM] Fix cmse_nonsecure_entry return insn size A number of instructions are output in assembler form by output_return_instruction () when compiling a function with the cmse_nonsecure_entry attribute for Armv8-M Mainline with hardfloat float ABI. However, the corresponding thumb2_cmse_entry_return insn pattern does not account for all these instructions in its computing of the length of the instruction. This may lead GCC to use the wrong branching instruction due to incorrect computation of the offset between the branch instruction's address and the target address. This commit fixes the mismatch between what output_return_instruction () does and what the pattern think it does and adds a note warning about mismatch in the affected functions' heading comments to ensure code does not get out of sync again. Note: no test is provided because the C testcase is fragile (only works on GCC 6) and the extracted RTL test fails to compile due to bugs in the RTL frontend (PR82815 and PR82817) 2017-11-09 Thomas Preud'homme gcc/ * config/arm/arm.c (output_return_instruction): Add comments to indicate requirement for cmse_nonsecure_entry return to account for the size of clearing instruction output here. (thumb_exit): Likewise. * config/arm/thumb2.md (thumb2_cmse_entry_return): Fix length for return in hardfloat mode. From-SVN: r254601 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b223f61b0d7..67d925c0014 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2017-11-09 Thomas Preud'homme + + * config/arm/arm.c (output_return_instruction): Add comments to + indicate requirement for cmse_nonsecure_entry return to account + for the size of clearing instruction output here. + (thumb_exit): Likewise. + * config/arm/thumb2.md (thumb2_cmse_entry_return): Fix length for + return in hardfloat mode. + 2017-11-09 Segher Boessenkool * config/rs6000/rs6000.c (machine_function): Add a bool, diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index c2a3e9ccbbf..f1ac70ff089 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -19417,7 +19417,12 @@ arm_get_vfp_saved_size (void) /* Generate a function exit sequence. If REALLY_RETURN is false, then do everything bar the final return instruction. If simple_return is true, - then do not output epilogue, because it has already been emitted in RTL. */ + then do not output epilogue, because it has already been emitted in RTL. + + Note: do not forget to update length attribute of corresponding insn pattern + when changing assembly output (eg. length attribute of + thumb2_cmse_entry_return when updating Armv8-M Mainline Security Extensions + register clearing sequences). */ const char * output_return_instruction (rtx operand, bool really_return, bool reverse, bool simple_return) @@ -23950,7 +23955,12 @@ thumb_pop (FILE *f, unsigned long mask) /* Generate code to return from a thumb function. If 'reg_containing_return_addr' is -1, then the return address is - actually on the stack, at the stack pointer. */ + actually on the stack, at the stack pointer. + + Note: do not forget to update length attribute of corresponding insn pattern + when changing assembly output (eg. length attribute of epilogue_insns when + updating Armv8-M Baseline Security Extensions register clearing + sequences). */ static void thumb_exit (FILE *f, int reg_containing_return_addr) { diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md index c2dcc8fddc0..abe90d4f4e4 100644 --- a/gcc/config/arm/thumb2.md +++ b/gcc/config/arm/thumb2.md @@ -1126,7 +1126,7 @@ ; we adapt the length accordingly. (set (attr "length") (if_then_else (match_test "TARGET_HARD_FLOAT") - (const_int 12) + (const_int 34) (const_int 8))) ; We do not support predicate execution of returns from cmse_nonsecure_entry ; functions because we need to clear the APSR. Since predicable has to be