From: lkcl <lkcl@web>
Date: Sat, 20 Aug 2022 14:43:13 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~821
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9f3131915b97ade5bfbdc50a70d3f0948616236e;p=libreriscv.git

---

diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn
index 1b5953d9c..be508e03d 100644
--- a/openpower/sv/ldst.mdwn
+++ b/openpower/sv/ldst.mdwn
@@ -79,6 +79,8 @@ More than that however it is necessary to fit the usual Vector ISA
 capabilities onto both Power ISA LD/ST with immediate and to
 LD/ST Indexed. They present subtly different Mode tables.
 
+# Format and fields
+
 Fields used in tables below:
 
 * **sz / dz**  if predication is enabled will put zeros into the dest (or as src in the case of twin pred) when the predicate bit is zero.  otherwise the element is ignored or skipped, depending on context.