From: lkcl <lkcl@web>
Date: Sat, 6 Nov 2021 11:41:05 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~3457
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9f31f4a3a5303e3815c7dbc21ce216d943e0ce03;p=libreriscv.git

---

diff --git a/openpower/sv/bitmanip.mdwn b/openpower/sv/bitmanip.mdwn
index 1ca77613f..1607384f2 100644
--- a/openpower/sv/bitmanip.mdwn
+++ b/openpower/sv/bitmanip.mdwn
@@ -67,8 +67,8 @@ minor opcode allocation
 
 | 0.5|6.10|11.15|16.20|21..25 | 26....30 |31| name |
 | -- | -- | --- | --- | ----- | -------- |--| ------ |
-| NN | RT | RA  | RB  | RC    | mode 001 |Rc| ternary |
-| NN | RT | RA  | RB  | im0-4 | im5-7 00 |Rc| ternaryi |
+| NN | RA | RS  | RB  | RC    | mode 001 |Rc| ternary |
+| NN | RA | RS  | RB  | im0-4 | im5-7 00 |Rc| ternaryi |
 | NN | RS | RA  | RB  | RC    | 00  011  |Rc| gfmul |
 | NN | RS | RA  | RB  | RC    | 01  011  |Rc| gfadd |
 | NN | RT | RA  | RB  | deg   | 10  011  |Rc| gfinv |
@@ -234,11 +234,11 @@ Similar to FPGA LUTs: for every bit perform a lookup into a table using an 8bit
 
 | 0.5|6.10|11.15|16.20| 21..25| 26..30   |31|
 | -- | -- | --- | --- | ----- | -------- |--|
-| NN | RT | RA  | RB  | im0-4 | im5-7 00 |Rc|
+| NN | RA | RS  | RB  | im0-4 | im5-7 00 |Rc|
 
     for i in range(64):
-        idx = RT[i] << 2 | RA[i] << 1 | RB[i]
-        RT[i] = (imm & (1<<idx)) != 0
+        idx = RS[i] << 2 | RB[i] << 1 | RA[i]
+        RA[i] = (imm & (1<<idx)) != 0
 
 bits 21..22 may be used to specify a mode, such as treating the whole integer zero/nonzero and putting 1/0 in the result, rather than bitwise test.
 
@@ -246,11 +246,11 @@ a 4 operand variant which becomes more along the lines of an FPGA:
 
 | 0.5|6.10|11.15|16.20|21.25| 26...30  |31|
 | -- | -- | --- | --- | --- | -------- |--|
-| NN | RT | RA  | RB  | RC  | mode 001 |Rc|
+| NN | RA | RS  | RB  | RC  | mode 001 |Rc|
 
     for i in range(64):
-        idx = RT[i] << 2 | RA[i] << 1 | RB[i]
-        RT[i] = (RC & (1<<idx)) != 0
+        idx = RS[i] << 2 | RB[i] << 1 | RA[i]
+        RA[i] = (RC & (1<<idx)) != 0
 
 mode (2 bit) may be used to do inversion of ordering, similar to carryless mul,
 3 modes.