From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 16 Jun 2020 17:16:53 +0000 (+0100)
Subject: add ports to TestMemory
X-Git-Tag: div_pipeline~361
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9f33eab664703a6537c0eea7dee43a0d0f116d33;p=soc.git

add ports to TestMemory
---

diff --git a/src/soc/experiment/testmem.py b/src/soc/experiment/testmem.py
index 7c753a0d..4821e21d 100644
--- a/src/soc/experiment/testmem.py
+++ b/src/soc/experiment/testmem.py
@@ -17,3 +17,14 @@ class TestMemory(Elaboratable):
         m.submodules.rdport = self.rdport
         m.submodules.wrport = self.wrport
         return m
+
+    def __iter__(self):
+        yield self.rdport.addr
+        yield self.rdport.data
+        yield self.rdport.en
+        yield self.wrport.addr
+        yield self.wrport.data
+        yield self.wrport.en
+
+    def ports(self):
+        return list(self)