From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Tue, 8 Aug 2017 03:33:08 +0000 (-0700)
Subject: Changed LEVEL resets to be edge triggered anyway
X-Git-Tag: yosys-0.8~346^2~3
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9f3dc59ffe5f585a55ee5a9e4ab7781c3e600513;p=yosys.git

Changed LEVEL resets to be edge triggered anyway
---

diff --git a/techlibs/greenpak4/cells_sim_digital.v b/techlibs/greenpak4/cells_sim_digital.v
index eb18a20b6..fc481975c 100644
--- a/techlibs/greenpak4/cells_sim_digital.v
+++ b/techlibs/greenpak4/cells_sim_digital.v
@@ -86,7 +86,7 @@ module GP_COUNT14(input CLK, input wire RST, output reg OUT);
 			end
 
 			"LEVEL": begin
-				always @(posedge CLK or RST) begin
+				always @(posedge CLK or posedge RST) begin
 					count		<= count - 1'd1;
 					if(count == 0)
 						count	<= COUNT_TO;
@@ -204,7 +204,7 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
 			end
 
 			"LEVEL": begin
-				always @(posedge CLK or RST) begin
+				always @(posedge CLK or posedge RST) begin
 
 					//Main counter
 					if(KEEP) begin
@@ -339,7 +339,7 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
 			end
 
 			"LEVEL": begin
-				always @(posedge CLK or RST) begin
+				always @(posedge CLK or posedge RST) begin
 
 					//Main counter
 					if(KEEP) begin
@@ -439,7 +439,7 @@ module GP_COUNT8(
 			end
 
 			"LEVEL": begin
-				always @(posedge CLK or RST) begin
+				always @(posedge CLK or posedge RST) begin
 					count		<= count - 1'd1;
 					if(count == 0)
 						count	<= COUNT_TO;