From: Samuel A. Falvo II <kc5tja@arrl.net>
Date: Mon, 3 Aug 2020 15:17:55 +0000 (-0700)
Subject: WIP: check MB > ME and select mask appropriately
X-Git-Tag: semi_working_ecp5~469
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9f3f2f99c48f3f18fb3b0978118adbdec3f627ea;p=soc.git

WIP: check MB > ME and select mask appropriately
---

diff --git a/src/soc/fu/shift_rot/formal/proof_main_stage.py b/src/soc/fu/shift_rot/formal/proof_main_stage.py
index fa1674f3..2f0455f4 100644
--- a/src/soc/fu/shift_rot/formal/proof_main_stage.py
+++ b/src/soc/fu/shift_rot/formal/proof_main_stage.py
@@ -185,7 +185,10 @@ class Driver(Elaboratable):
                 # code norms.
 
                 mrl = Signal(64, reset_less=True, name='MASK_FOR_RLC')
-                comb += mrl.eq(ml | mr)
+                with m.If(mb > me):
+                    comb += mrl.eq(ml | mr)
+                with m.Else():
+                    comb += mrl.eq(ml & mr)
 
                 ainp = Signal(64, reset_less=True, name='A_INP_FOR_RLC')
                 comb += ainp.eq(field(a, 32, 63))