From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 9 Apr 2021 11:57:51 +0000 (+0100)
Subject: make main.cpp general-purpose (#define module)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9f470274075412db5c857b6eaff98bb440a77097;p=soc-cxxrtl-sim.git

make main.cpp general-purpose (#define module)
---

diff --git a/ls180_test/Makefile b/ls180_test/Makefile
index b8eed8e..453c6ce 100644
--- a/ls180_test/Makefile
+++ b/ls180_test/Makefile
@@ -3,7 +3,6 @@ YOSYS			= yosys
 YOSYS_INCLUDE	= $(shell yosys-config --datdir)/include
 
 all: tb
-	./tb
 
 tb: main.cpp ls180.cpp
 	clang++ -g -O3 -std=c++14 -I $(YOSYS_INCLUDE) $< -o $@
diff --git a/small_jtag_test/Makefile b/small_jtag_test/Makefile
index 4cc26cc..2124e97 100644
--- a/small_jtag_test/Makefile
+++ b/small_jtag_test/Makefile
@@ -6,7 +6,10 @@ all: tb
 	./tb
 
 tb: main.cpp add.cpp
-	clang++ -g -O3 -std=c++14 -I $(YOSYS_INCLUDE) $< -o $@
+	clang++ \
+    -DDESIGN=cxxrtl_design::p_add \
+    -DCXX_FILE=\"add.cpp\" \
+    -g -O3 -std=c++14 -I $(YOSYS_INCLUDE) $< -o $@
 
 add.cpp: add.v
 	$(YOSYS) -p "read_verilog $<; write_cxxrtl $@"
diff --git a/small_jtag_test/add.py b/small_jtag_test/add.py
index aa7b487..7cbabb9 100644
--- a/small_jtag_test/add.py
+++ b/small_jtag_test/add.py
@@ -1,7 +1,7 @@
 # generate add.il ilang file with: python3 add.py
 #
 
-from nmigen import Elaboratable, Signal, Module, Const
+from nmigen import Elaboratable, Signal, Module, Const, DomainRenamer
 from nmigen.cli import verilog
 
 # to get c4m-jtag
@@ -20,10 +20,10 @@ class ADD(Elaboratable):
 
         # set up JTAG
         self.jtag = TAP(ir_width=4)
-        self.jtag.bus.tck.name = 'tck'
-        self.jtag.bus.tms.name = 'tms'
-        self.jtag.bus.tdo.name = 'tdo'
-        self.jtag.bus.tdi.name = 'tdi'
+        self.jtag.bus.tck.name = 'jtag_tck'
+        self.jtag.bus.tms.name = 'jtag_tms'
+        self.jtag.bus.tdo.name = 'jtag_tdo'
+        self.jtag.bus.tdi.name = 'jtag_tdi'
 
         # have to create at least one shift register
         self.sr = self.jtag.add_shiftreg(ircode=4, length=3)
@@ -44,14 +44,14 @@ class ADD(Elaboratable):
         return m
 
 
-def create_ilang(dut, ports, test_name):
+def create_verilog(dut, ports, test_name):
     vl = verilog.convert(dut, name=test_name, ports=ports)
     with open("%s.v" % test_name, "w") as f:
         f.write(vl)
 
 if __name__ == "__main__":
-    alu = ADD(width=4)
-    create_ilang(alu, [alu.a, alu.b, alu.f,
+    alu = DomainRenamer("sys")(ADD(width=4))
+    create_verilog(alu, [alu.a, alu.b, alu.f,
                        alu.jtag.bus.tck,
                         alu.jtag.bus.tms,
                         alu.jtag.bus.tdo,
diff --git a/small_jtag_test/main.cpp b/small_jtag_test/main.cpp
index 987b742..d53126b 100644
--- a/small_jtag_test/main.cpp
+++ b/small_jtag_test/main.cpp
@@ -14,7 +14,7 @@
 #include <iostream>
 #include <fstream>
 
-#include "add.cpp"
+#include CXX_FILE
 
 #define VCD
 
@@ -124,7 +124,7 @@ int read_handler(int fdread, char *buffer)
    indicates that receiver wants to know the status of TDO.
    "Q" means "quit socket".
 */
-int read_openocd_jtagremote(cxxrtl_design::p_add &top, int sock)
+int read_openocd_jtagremote(DESIGN &top, int sock)
 {
     char c;
     if (read_handler(sock, &c) != 1) {
@@ -133,13 +133,13 @@ int read_openocd_jtagremote(cxxrtl_design::p_add &top, int sock)
     printf ("read %c\n", c);
     if ((c >= '0') && (c <= '7'))
     {
-        top.p_tck.set<bool>(((c - '0') >> 2) & 1);
-        top.p_tms.set<bool>(((c - '0') >> 1) & 1);
-        top.p_tdi.set<bool>((c - '0')  & 1);
+        top.p_jtag__tck.set<bool>(((c - '0') >> 2) & 1);
+        top.p_jtag__tms.set<bool>(((c - '0') >> 1) & 1);
+        top.p_jtag__tdi.set<bool>((c - '0')  & 1);
     }
     if (c == 'R')
     {
-        uint8_t val = top.p_tdo.get<uint8_t>() + '0';
+        uint8_t val = top.p_jtag__tdo.get<uint8_t>() + '0';
         if(-1 == write(sock, &val, 1))
         {
             printf("Error writing on socket\n");
@@ -157,7 +157,7 @@ int read_openocd_jtagremote(cxxrtl_design::p_add &top, int sock)
 
 int main()
 {
-    cxxrtl_design::p_add top;
+    DESIGN top;
     int steps = 0;
 
 #ifdef VCD
@@ -185,12 +185,12 @@ int main()
 #endif
     while (true) {
 
-        top.p_clk.set<bool>(false);
+        top.p_sys__clk.set<bool>(false);
         top.step();
 #ifdef VCD
         vcd.sample(steps*2 + 0);
 #endif
-        top.p_clk.set<bool>(true);
+        top.p_sys__clk.set<bool>(true);
         top.step();
 #ifdef VCD
         vcd.sample(steps*2 + 1);
@@ -204,15 +204,6 @@ int main()
         /* read and process incoming jtag. sock set to -1 if disconnected */
         sock = read_openocd_jtagremote(top, sock);
 
-        // quick check that the output is correct (it's an adder: go figure)
-        /*
-        top.p_a.set<uint8_t>(5);
-        top.p_b.set<uint8_t>(3);
-        uint32_t f    = top.p_f.get<uint32_t>();
-
-        cout << "f " << f << endl;
-        */
-
         waves << vcd.buffer;
         vcd.buffer.clear();
     }