From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 8 Nov 2013 10:06:11 +0000 (+0100)
Subject: Fixed handling of different signedness in power operands
X-Git-Tag: yosys-0.2.0~379
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9f49d538e1e6bd59c848f19226c95949ba2f37b5;p=yosys.git

Fixed handling of different signedness in power operands
---

diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 9fa7f558b..fdb6e9edd 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -1020,7 +1020,7 @@ skip_dynamic_range_lvalue_expansion:;
 		if (0) { case AST_POW:          const_func = RTLIL::const_pow; }
 			if (children[0]->type == AST_CONSTANT && children[1]->type == AST_CONSTANT) {
 				RTLIL::Const y = const_func(children[0]->bitsAsConst(width_hint, sign_hint),
-						RTLIL::Const(children[1]->bits), sign_hint, type == AST_POW ? sign_hint : false, width_hint);
+						RTLIL::Const(children[1]->bits), sign_hint, type == AST_POW ? children[1]->is_signed : false, width_hint);
 				newNode = mkconst_bits(y.bits, sign_hint);
 			}
 			break;