From: lkcl <lkcl@web>
Date: Thu, 5 May 2022 14:16:39 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2448
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9f4c24cb5378d6a76950b84901b3ac87fc613dbe;p=libreriscv.git

---

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index 56c96c786..57a3bca3f 100644
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -43,4 +43,17 @@ reviving Cray Vectors, has severe performance and imolementation
 limitations that are only really apparent to exceptionally experienced
 assembly-level developers with a wide, diverse depth in multiple ISAs:
 one of the best and clearest is a
-[ycombinator post](
+[ycombinator post](https://news.ycombinator.com/item?id=24459041)
+by adrian_b.
+
+Adrian logically and concisely points out that the fundamental
+design assumptions and
+simplifications that went into the RISC-V ISA have an
+irrevocably damaging effect
+on its viability for high performance use.  That is not to say that
+its use in low-performance embedded scenarios is not ideal: in
+private custom secretive commercial usage it is perfect. Ubiquitous
+and common everyday usage in scenarios currently occupied by ARM, Intel,
+AMD and IBM: not so much. Thus, even though RISC-V has Cray-style Vectors,
+the ISA is, unfortunately, fundamentally flawed.
+