From: Cotton Seed Date: Sun, 6 Dec 2015 22:24:48 +0000 (-0500) Subject: Added LO to ICESTORM_LC for LUT cascade route. X-Git-Tag: yosys-0.6~52^2 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9f5b6e4cbc4da0b3ae6429b03097532de3bf4c60;p=yosys.git Added LO to ICESTORM_LC for LUT cascade route. --- diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index 17b6be9ce..f94040245 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -661,7 +661,7 @@ endmodule module ICESTORM_LC ( input I0, I1, I2, I3, CIN, CLK, CEN, SR, - output O, COUT + output LO, O, COUT ); parameter [15:0] LUT_INIT = 0; @@ -678,6 +678,8 @@ module ICESTORM_LC ( wire [1:0] lut_s1 = I1 ? lut_s2[ 3:2] : lut_s2[1:0]; wire lut_o = I0 ? lut_s1[ 1] : lut_s1[ 0]; + assign LO = lut_o; + wire polarized_clk; assign polarized_clk = CLK ^ NEG_CLK;