From: whitequark <whitequark@whitequark.org>
Date: Sun, 16 Dec 2018 18:25:53 +0000 (+0000)
Subject: Update CHANGELOG.
X-Git-Tag: yosys-0.9~367^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9f5c7017ff89ad914b6b9be0620996d77e24f71b;p=yosys.git

Update CHANGELOG.
---

diff --git a/CHANGELOG b/CHANGELOG
index a00c2adf8..42e01645e 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -9,6 +9,13 @@ Yosys 0.8 .. Yosys 0.8-dev
  * Various
     - Added $changed support to read_verilog
     - Added "write_edif -attrprop"
+    - Added "ice40_unlut" pass
+    - Added "opt_lut" pass
+    - Added "synth_ice40 -relut"
+    - Added "synth_ice40 -noabc"
+    - Added "gate2lut.v" techmap rule
+    - Added "rename -src"
+    - Added "equiv_opt" pass
 
 
 Yosys 0.7 .. Yosys 0.8