From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 11 Jul 2019 03:25:59 +0000 (-0700)
Subject: write_verilog with *.v extension
X-Git-Tag: working-ls180~881^2^2~266
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9f608d6be30c9302c0e3810525457e39f57b0334;p=yosys.git

write_verilog with *.v extension
---

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 6e57ab7f3..330361f65 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -435,7 +435,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 		//		count_gates, GetSize(signal_list), count_input, count_output);
 
 #if 0
-		Pass::call(design, stringf("write_verilog -noexpr -norename %s/before.xaig", tempdir_name.c_str()));
+		Pass::call(design, stringf("write_verilog -noexpr -norename %s/before.v", tempdir_name.c_str()));
 #endif
 		Pass::call(design, stringf("write_xaiger -map %s/input.sym %s/input.xaig", tempdir_name.c_str(), tempdir_name.c_str()));