From: Luke Kenneth Casson Leighton Date: Sat, 3 Jun 2023 18:31:33 +0000 (+0100) Subject: fix (most) unit tests in test_pysvp64dis.py X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9f8828dd7cd573a086f7502f364009fa7199e181;p=openpower-isa.git fix (most) unit tests in test_pysvp64dis.py the fields in/out are sorted (https://bugs.libre-soc.org/show_bug.cgi?id=1098) but it looks like rldimi is the wrong bit-pattern --- diff --git a/src/openpower/sv/trans/test_pysvp64dis.py b/src/openpower/sv/trans/test_pysvp64dis.py index 58d41d14..8aea032a 100644 --- a/src/openpower/sv/trans/test_pysvp64dis.py +++ b/src/openpower/sv/trans/test_pysvp64dis.py @@ -1,5 +1,5 @@ from openpower.simulator.program import Program -from openpower.insndb.disam import load, dump +from openpower.insndb.disasm import load, dump from openpower.insndb.asm import SVP64Asm from openpower.insndb.core import Database, Style from openpower.decoder.power_enums import find_wiki_dir @@ -35,7 +35,7 @@ class SVSTATETestCase(unittest.TestCase): "'%s' expected '%s'" % (line, expected[i])) - def tst_0_add(self): + def test_0_add(self): expected = ['addi 1,5,2', 'add 1,5,2', 'add. 1,5,2', @@ -44,13 +44,13 @@ class SVSTATETestCase(unittest.TestCase): ] self._do_tst(expected) - def tst_1_svshape2(self): + def test_1_svshape2(self): expected = [ 'svshape2 12,1,15,5,0,0' ] self._do_tst(expected) - def tst_2_d_custom_op(self): + def test_2_d_custom_op(self): expected = [ 'fishmv 12,2', 'fmvis 12,97', @@ -58,7 +58,7 @@ class SVSTATETestCase(unittest.TestCase): ] self._do_tst(expected) - def tst_3_sv_isel(self): + def test_3_sv_isel(self): expected = [ 'sv.isel 12,2,3,33', 'sv.isel 12,2,3,*33', @@ -68,7 +68,7 @@ class SVSTATETestCase(unittest.TestCase): ] self._do_tst(expected) - def tst_4_sv_crand(self): + def test_4_sv_crand(self): expected = [ 'sv.crand *16,*2,*33', 'sv.crand 12,2,33', @@ -79,21 +79,21 @@ class SVSTATETestCase(unittest.TestCase): ] self._do_tst(expected) - def tst_5_setvl(self): + def test_5_setvl(self): expected = [ "setvl 5,4,5,0,1,1", "setvl. 5,4,5,0,1,1", ] self._do_tst(expected) - def tst_6_sv_setvl(self): + def test_6_sv_setvl(self): expected = [ "sv.setvl 5,4,5,0,1,1", "sv.setvl 63,35,5,0,1,1", ] self._do_tst(expected) - def tst_7_batch(self): + def test_7_batch(self): "these come from https://bugs.libre-soc.org/show_bug.cgi?id=917#c25" expected = [ "addi 2,2,0", @@ -167,7 +167,7 @@ class SVSTATETestCase(unittest.TestCase): ] self._do_tst(expected) - def tst_8_madd(self): + def test_8_madd(self): expected = [ "maddhd 5,4,5,3", "maddhdu 5,4,5,3", @@ -175,7 +175,7 @@ class SVSTATETestCase(unittest.TestCase): ] self._do_tst(expected) - def tst_9_fptrans(self): + def test_9_fptrans(self): "enumerates a list of fptrans instruction disassembly entries" db = Database(find_wiki_dir()) entries = sorted(sv_binutils_fptrans.collect(db)) @@ -186,7 +186,7 @@ class SVSTATETestCase(unittest.TestCase): lst.append(line) self._do_tst(lst) - def tst_10_vec(self): + def test_10_vec(self): expected = [ "sv.add./vec2 *3,*7,*11", "sv.add./vec3 *3,*7,*11", @@ -194,7 +194,7 @@ class SVSTATETestCase(unittest.TestCase): ] self._do_tst(expected) - def tst_11_elwidth(self): + def test_11_elwidth(self): expected = [ "sv.add./dw=8 *3,*7,*11", "sv.add./dw=16 *3,*7,*11", @@ -211,14 +211,14 @@ class SVSTATETestCase(unittest.TestCase): ] self._do_tst(expected) - def tst_12_sat(self): + def test_12_sat(self): expected = [ "sv.add./satu *3,*7,*11", "sv.add./sats *3,*7,*11", ] self._do_tst(expected) - def tst_12_mr_r(self): + def test_12_mr_r(self): expected = [ "sv.add./mrr/vec2 *3,*7,*11", "sv.add./mr/vec2 *3,*7,*11", @@ -227,14 +227,14 @@ class SVSTATETestCase(unittest.TestCase): ] self._do_tst(expected) - def tst_13_RC1(self): + def test_13_RC1(self): expected = [ "sv.add/ff=RC1 *3,*7,*11", "sv.add/ff=~RC1 *3,*7,*11", ] self._do_tst(expected) - def tst_14_rc1_ff_pr(self): + def test_14_rc1_ff_pr(self): expected = [ "sv.add./ff=eq *3,*7,*11", "sv.add./ff=ns *3,*7,*11", @@ -246,7 +246,7 @@ class SVSTATETestCase(unittest.TestCase): ] self._do_tst(expected) - def tst_15_predicates(self): + def test_15_predicates(self): expected = [ "sv.add./m=r3 *3,*7,*11", "sv.add./m=1<