From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 6 Mar 2020 17:01:35 +0000 (+0000)
Subject: add ioring.py (forgot about)
X-Git-Tag: partial-core-ls180-gdsii~176
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9fc5659b125af88c23d7257158dcad08b696f352;p=soclayout.git

add ioring.py (forgot about)
---

diff --git a/experiments4/coriolis2/ioring.py b/experiments4/coriolis2/ioring.py
new file mode 100644
index 0000000..2227b20
--- /dev/null
+++ b/experiments4/coriolis2/ioring.py
@@ -0,0 +1,14 @@
+#!/usr/bin/env python
+
+from helpers import l, u, n
+
+
+chip = { 'pads.ioPadGauge' : 'pxlib'
+       , 'pads.south'      : [ 'a_1', 'p_vddick_0', 'p_vssick_0' , 'a_0'       ]
+       , 'pads.east'       : [ 'a_2', 'a_3'       , 'b_3'        , 'b_2'       ]
+       , 'pads.north'      : [ 'b_1', 'p_vddeck_0', 'b_0'        , 'p_vsseck_0', 'rst' ]
+       , 'pads.west'       : [ 'f_3', 'f_2'       , 'p_clk_0', 'f_1'       , 'f_0'     ]
+       , 'core.size'       : ( l( 800), l( 800) )
+       , 'chip.size'       : ( l(2000), l(2000) )
+       , 'chip.clockTree'  : True
+       }