From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Tue, 3 May 2016 03:29:39 +0000 (-0700)
Subject: Added comment to clarify GP_ABUF cell
X-Git-Tag: yosys-0.7~235^2~4
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9fc9d5f1fb1eea47118c00ecad1352ec84fd3047;p=yosys.git

Added comment to clarify GP_ABUF cell
---

diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v
index 04bce8771..7555a7ac8 100644
--- a/techlibs/greenpak4/cells_sim.v
+++ b/techlibs/greenpak4/cells_sim.v
@@ -17,6 +17,8 @@ module GP_ABUF(input wire IN, output wire OUT);
 	
 	assign OUT = IN;
 	
+	//cannot simulate mixed signal IP
+	
 endmodule
 
 module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg OUT);