From: lkcl <lkcl@web>
Date: Mon, 16 Aug 2021 10:45:34 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~436
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9fe2827865ff11da7cdddd31e60c7e741768bc39;p=libreriscv.git

---

diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn
index 3f499587d..337953a7b 100644
--- a/openpower/sv/setvl.mdwn
+++ b/openpower/sv/setvl.mdwn
@@ -118,8 +118,11 @@ the same instruction.  That would require two instructions.
 
 In Vertical-First Mode the minimum expectation is that one scalar
 element may be executed by each instruction. There are however
-circumstances where it may be possible to execute more than one:
-determining a "safe minimum amount" may not be practical.
+circumstances where it may be possible to execute more than one
+element per instruction (srcstep elements 0-3 for example)
+but leaving it up to hardware to
+determine a "safe minimum amount" where memory corruption does
+not occur may not be practical (or is simply very costly).
 
 Therefore, setmvlhi may specify, as determined by the compiler,
 exactly what that quantity is.  Unlike VL, which is an amount