From: Andreas Hansson <andreas.hansson@arm.com>
Date: Fri, 14 Nov 2014 08:53:48 +0000 (-0500)
Subject: mem: Clarify unit of DRAM controller buffer size
X-Git-Tag: stable_2015_04_15~131
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9ffe0e7ba67ee194db885b96a7ed3630aed03584;p=gem5.git

mem: Clarify unit of DRAM controller buffer size
---

diff --git a/src/mem/DRAMCtrl.py b/src/mem/DRAMCtrl.py
index 642e9d525..74fb7c7be 100644
--- a/src/mem/DRAMCtrl.py
+++ b/src/mem/DRAMCtrl.py
@@ -71,7 +71,10 @@ class DRAMCtrl(AbstractMemory):
     # bus in front of the controller for multiple ports
     port = SlavePort("Slave port")
 
-    # the basic configuration of the controller architecture
+    # the basic configuration of the controller architecture, note
+    # that each entry corresponds to a burst for the specific DRAM
+    # configuration (e.g. x32 with burst length 8 is 32 bytes) and not
+    # the cacheline size or request/packet size
     write_buffer_size = Param.Unsigned(64, "Number of write queue entries")
     read_buffer_size = Param.Unsigned(32, "Number of read queue entries")